XOR-CIM: Compute-In-Memory SRAM Architecture with Embedded XOR Encryption. - Shanshi Huang; Hongwu Jiang; Xiaochen Peng; Wantong Li 002; Shimeng Yu (ICCAD, 2020)

NeuroSim Validation with 40nm RRAM Compute-in-Memory Macro. - Anni Lu; Xiaochen Peng; Wantong Li 002; Hongwu Jiang; Shimeng Yu (AICAS, 2021)

Secure-RRAM: A 40nm 16kb Compute-in-Memory Macro with Reconfigurability, Sparsity Control, and Embedded Security. - Wantong Li 002; Shanshi Huang; Xiaoyu Sun 001; Hongwu Jiang; Shimeng Yu (CICC, 2021)

A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References. - Wantong Li 002; Xiaoyu Sun 001; Hongwu Jiang; Shanshi Huang; Shimeng Yu (ESSCIRC, 2021)

Compute-in-Memory: From Device Innovation to 3D System Integration. - Shimeng Yu; Wonbo Shim; Jae Hur; Yuan-chun Luo; Gihun Choe; Wantong Li 002; Anni Lu; Xiaochen Peng (ESSDERC, 2021)

NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark. - Anni Lu; Xiaochen Peng; Wantong Li 002; Hongwu Jiang; Shimeng Yu (Frontiers Artif. Intell., 2021)

Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption. - Shanshi Huang; Hongwu Jiang; Xiaochen Peng; Wantong Li 002; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Temporal Frame Filtering with Near-Pixel Compute for Autonomous Driving. - Wantong Li 002; Qiucheng Wu; Janak Sharda; Shiyu Chang; Shimeng Yu (AICAS, 2022)

A 40nm RRAM Compute-in-Memory Macro with Parallelism-Preserving ECC for Iso-Accuracy Voltage Scaling. - Wantong Li 002; James Read; Hongwu Jiang; Shimeng Yu (ESSCIRC, 2022)

A Method for Reverse Engineering Neural Network Parameters from Compute-in-Memory Accelerators. - James Read; Wantong Li 002; Shimeng Yu (ISVLSI, 2022)

A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays. - Hongwu Jiang; Wantong Li 002; Shanshi Huang; Shimeng Yu (VLSI Technology and Circuits, 2022)

Analog-to-Digital Converter Design Exploration for Compute-in-Memory Accelerators. - Hongwu Jiang; Wantong Li 002; Shanshi Huang; Stefan Cosemans; Francky Catthoor; Shimeng Yu (IEEE Des. Test, 2022)

MAC-ECC: In-Situ Error Correction and Its Design Methodology for Reliable NVM-Based Compute-in-Memory Inference Engine. - Wantong Li 002; James Read; Hongwu Jiang; Shimeng Yu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References. - Wantong Li 002; Xiaoyu Sun 001; Shanshi Huang; Hongwu Jiang; Shimeng Yu (IEEE J. Solid State Circuits, 2022)

Optimization Strategies for Digital Compute-in-Memory from Comparative Analysis with Systolic Array. - Wantong Li 002; Junmo Lee; Shimeng Yu (AICAS, 2023)

Enabling Ultra-Low Power Ultrasound Imaging with Compute-in-Memory Sparse Reconstruction Accelerator. - Wantong Li 002; Xitie Zhang; Junmo Lee; F. Levent Degertekin; Shaolan Li; Shimeng Yu (BioCAS, 2023)

RAWAtten: Reconfigurable Accelerator for Window Attention in Hierarchical Vision Transformers. - Wantong Li 002; Yandong Luo; Shimeng Yu (DATE, 2023)

Enabling Long-Term Robustness in RRAM-based Compute-In-Memory Edge Devices. - James Read; Wantong Li 002; Shimeng Yu (ISCAS, 2023)

A Reconfigurable Monolithic 3D Switched-Capacitor DC-DC Converter with Back-End-of-Line Oxide Channel Transistor. - Jungyoun Kwak; Wantong Li 002; Shimeng Yu (MWSCAS, 2023)

ENNA: An Efficient Neural Network Accelerator Design Based on ADC-Free Compute-In-Memory Subarrays. - Hongwu Jiang; Shanshi Huang; Wantong Li 002; Shimeng Yu (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Temporal Frame Filtering for Autonomous Driving Using 3D-Stacked Global Shutter CIS With IWO Buffer Memory and Near-Pixel Compute. - Janak Sharda; Wantong Li 002; Qiucheng Wu; Shiyu Chang; Shimeng Yu (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory Accelerator for Vision Transformer Self-Attention. - Wantong Li 002; Madison Manley; James Read; Ankit Kaul; Muhannad S. Bakir; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2023)

NeuroSim V1.4: Extending Technology Support for Digital Compute-in-Memory Toward 1nm Node. - Junmo Lee; Anni Lu; Wantong Li 002; Shimeng Yu (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

RandEye: On-Sensor Stochastic Image Transformation for Backdoor-Resistant Edge Inference. - Wantong Li 002; Liuwan Zhu (ACM Great Lakes Symposium on VLSI, 2025)

Folded Banks: 3D-Stacked HBM Design for Fine-Grained Random-Access Bandwidth. - Vignesh Adhinarayanan; Bradford M. Beckmann; Wantong Li 002; Mohammad Seyedzadeh; Sergey Blagodurov; Derrick Aguren; Hayden Hyungdong Lee (ISCA, 2025)

DarkFlow: Hierarchical Digital SiPM Architecture with Low-Loss Dataflow Readout for Dark Matter Detection. - Zirui Wang; Aras Repond; Shawn Westerdale; Wantong Li 002 (ACM Great Lakes Symposium on VLSI, 2026)