Yield aware inter-logic-layer communication in 3-D ICs: Early design stage recommendations. - Waqas Gul; Syed Rafay Hasan; Osman Hasan (MWSCAS, 2014)

Clock domain crossing (CDC) for inter-logic-layer communication in 3-D ICs. - Waqas Gul; Syed Rafay Hasan; Osman Hasan (NEWCAS, 2014)

Synchronously triggered GALS design templates leveraging QDI asynchronous interfaces. - Waqas Gul; Syed Rafay Hasan; Osman Hasan; Faiq Khalid Lodhi; Falah R. Awwad (ISCAS, 2016)

Clock domain crossing (CDC) in 3D-SICs: Semi QDI asynchronous vs loosely synchronous. - Syed Rafay Hasan; Waqas Gul; Osman Hasan (Integr., 2016)

FinFET 6T-SRAM Compute-in-Memory Targeting Low Power Neural Networks Operations. - Waqas Gul; Maitham Shams; Dhamin Al-Khalili (ISCAS, 2023)