A 9.95 to 11.1Gb/s XFP transceiver in 0.13µm CMOS. - Jack Kenney; Declan Dalton; Murat Hayri Eskiyerli; Eric Evans; Barry Hilton; Dave Hitchcox; Terence Kwok; Daniel Mulcahy; Chris McQuilkin; Viswabharath Reddy; Siva Selvanayagam; Paul Shepherd; et al. (ISSCC, 2006)

A 9.95-11.3-Gb/s XFP Transceiver in 0.13-$ mu{ hbox {m}}$ CMOS. - John G. Kenney; Declan Dalton; Eric Evans; Murat Hayri Eskiyerli; Barry Hilton; Dave Hitchcox; Terence Kwok; Daniel Mulcahy; Chris McQuilkin; Viswabharath Reddy; Siva Selvanayagam; Paul Shepherd; et al. (IEEE J. Solid State Circuits, 2006)

A 5.6 GHz to 11.5 GHz DCO for Digital Dual Loop CDRs. - Ward S. Titus; John G. Kenney (IEEE J. Solid State Circuits, 2012)

A 6.5Mb/s to 11.3Gb/s continuous-rate clock and data recovery. - Jack Kenney; Terry Chen; Larry DeVito; Declan Dalton; Stuart McCracken; Richard Soenneker; Ward S. Titus; Todd S. Weigandt (CICC, 2014)

A 12.5-Gb/s self-calibrating linear phase detector-based CDR using 0.18μm SiGe BiCMOS. - Jeremy Walker; John G. Kenney; Jesse Bankman; Terry Chen; Steve Harston; Kenneth Lawas; Andrew Lewine; Richard Soenneker; Michael St. Germain; Ward S. Titus; Andrew Y. Wang; Kimo Tam (CICC, 2014)