A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register. - Kazutami Arimoto; Kazuyasu Fujishima; Yoshio Matsuda; Masaki Tsukude; Tukasa Oishi; Wataru Wakamiya; Shin'ichi Satoh 004; Michihiro Yamada; Takao Nakano (IEEE J. Solid State Circuits, 1989)

A 34-ns 16-Mb DRAM with controllable voltage down-converter. - Hideto Hidaka; Kazutami Arimoto; Kazutoshi Hirayama; Masanori Hayashikoshi; Mikio Asakura; Masaki Tsukude; Tsukasa Oishi; Shinji Kawai; Katsuhiro Suma; Yasuhiro Konishi; Koji Tanaka; Wataru Wakamiya; et al. (IEEE J. Solid State Circuits, 1992)

Novel via Chain Structure for Failure Analysis at 65 nm-Node Fixing OPC Using Inner and Outer via Chain Dummy Patterns. - Takashi Nasuno; Yoshihisa Matsubara; Hiromasa Kobayashi; Akiyuki Minami; Eiichi Soda; Hiroshi Tsuda; Koichiro Tsujita; Wataru Wakamiya; Nobuyoshi Kobayashi (IEICE Trans. Electron., 2005)