The suggestion for CFS CMOS buffer. - Kuo-Hsing Cheng; Wei-Bin Yang (ICECS, 1999)

A CMOS low power voltage controlled oscillator with split-path controller. - Kuo-Hsing Cheng; Lin-Jiunn Tzou; Wei-Bin Yang; Shyh-Shyuan Sheu (ICECS, 2001)

A difference detector PFD for low jitter PLL. - Kuo-Hsing Cheng; Tse-Hua Yao; Shu-Yu Jiang; Wei-Bin Yang (ICECS, 2001)

A low-power high driving ability voltage control oscillator used in PLL. - Kuo-Hsing Cheng; Wei-Bin Yang; Chun-Fu Chung (ISCAS (4), 2001)

A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loop. - Kuo-Hsing Cheng; Wei-Bin Yang; Cheng-Ming Ying (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop. - Kuo-Hsing Cheng; Wei-Bin Yang; Shu-Chang Kuo (ISCAS (1), 2004)

The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle. - Wei-Bin Yang; Shu-Chang Kuo; Yuan-Hua Chu; Kuo-Hsing Cheng (ECCTD, 2005)

A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit. - Kuo-Hsing Cheng; Shu-Ming Chang; Shu-Yu Jiang; Wei-Bin Yang (ISCAS (2), 2005)

Analysis and Design of High Performance, Low Power Multiple Ports Register Files. - Ting-Sheng Jau; Wei-Bin Yang; Chung-Yu Chang (APCCAS, 2006)

A Variable Duty Cycle with High-Resolution Synchronous Mirror Delay. - Kai-Wei Hong; Chien-Hsien Lee; Kuo-Hsing Cheng; Chen-Lung Wu; Wei-Bin Yang (ICECS, 2006)

A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler. - Ting-Sheng Jau; Wei-Bin Yang; Yu-Lung Lo (ICECS, 2006)

The new improved pseudo fractional-N clock generator with 50% duty cycle. - Shu-Chang Kuo; Tzu-Chien Hung; Wei-Bin Yang (ISCAS, 2006)

A 100 MHz-1 GHz Adaptive Bandwidth PLL Using TDC Technique. - Kuo-Hsing Cheng; Yu-Lung Lo; Ching-Wen Lai; Wei-Bin Yang (ICECS, 2007)

New Power Gating Structure with Low Voltage Fluctuations by Bulk Controller in Transition Mode. - Chung-Yu Chang; Wei-Bin Yang; Ching-Ji Huang; Cheng-Hsing Chien (ISCAS, 2007)

A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III. - Kuo-Hsing Cheng; Cheng-Liang Hung; Chih-Hsien Chang; Yu-Lung Lo; Wei-Bin Yang; Jiunn-Way Miaw (DDECS, 2008)

0.5V 160-MHz 260uW all digital phase-locked loop. - Jen-Chieh Liu; Hong-Yi Huang; Wei-Bin Yang; Kuo-Hsing Cheng (DDECS, 2009)

Designing ultra-low voltage PLL Using a bulk-driven technique. - Ting-Sheng Chao; Yu-Lung Lo; Wei-Bin Yang; Kuo-Hsing Cheng (ESSCIRC, 2009)

High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer. - Yu-Lung Lo; Wei-Bin Yang; Ting-Sheng Chao; Kuo-Hsing Cheng (IEICE Trans. Electron., 2009)

Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique. - Yu-Lung Lo; Wei-Bin Yang; Ting-Sheng Chao; Kuo-Hsing Cheng (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A Pseudo Fractional-N Clock Generator with 50% Duty Cycle Output. - Wei-Bin Yang; Yu-Lung Lo; Ting-Sheng Chao (IEICE Trans. Electron., 2010)

A new temperature independent current controlled oscillator. - Zheng-Yi Huang; Jen-Shiun Chiang; Wei-Bin Yang; Chi-Hsiung Wang (ISPACS, 2011)

A synthesizable pseudo fractional-N clock generator with improved duty cycle output. - Wei-Bin Yang; Chang-Yo Hsieh (Microelectron. J., 2011)

A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process. - Wei-Bin Yang; Chao-Cheng Liao; Yung-Chih Liang (Microelectron. J., 2011)

A 300 mV 10 MHz 4 kb 10T subthreshold SRAM for ultralow-power application. - Wei-Bin Yang; Chi-Hsiung Wang; I-Ting Chuo; Huang-Hsuan Hsu (ISPACS, 2012)

A GHz full-division-range programmable divider with output duty-cycle improved. - Yu-Lung Lo; Jhih-Wei Tsai; Han-Ying Liu; Wei-Bin Yang (DDECS, 2013)

A multiple frequency clock generator using wide operation frequency range phase interpolator. - Wei-Bin Yang; Chi-Hsiung Wang; Sheng-Shih Yeh; Chao-Cheng Liao (Microelectron. J., 2013)

Analysis and design considerations of static CMOS logics under process, voltage and temperature variation in UMC 0.18µm CMOS process. - Wei-Bin Yang; Yu-Yao Lin; Chi-Hsiung Wang; Kuo-Ning Chang; Cing-Huan Chen; Yu-Lung Lo (ISPACS, 2015)

A 25 MHz crystal less clock generator with background calibration against process and temperature variation. - Wei-Bin Yang; Ming-Hao Hong (Comput. Electr. Eng., 2016)

Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input. - Wei-Bin Yang; Yu-Yao Lin; Yu-Lung Lo (Circuits Syst. Signal Process., 2017)

A Selectable Discrete-Voltage Output and Fast-Settling Low-Dropout Regulator Using Half Digitally-Assistant Voltage Accelerator. - Wei-Bin Yang; Ming-Hao Hong; Jsung Mo Shen (J. Signal Process. Syst., 2017)

Asynchronous Domino Binary search Digital LDO. - Wei-Bin Yang; Shu-Yu Ku; Chun-Wei Wang; Li-Lun Chu (ISPACS, 2021)

Asynchronous Digital Low-Dropout Regulator With Dual Adjustment Mode in Ultra-Low Voltage Input. - Wei-Bin Yang; Chi-Hsuan Sun; Diptendu Sinha Roy; Yi-Mei Chen (IEEE Access, 2021)

Instrumentation of Twin-MCMs based mutual-test. - Shun Shen Peter Wang; Yin-Tien Wang; Choung-Lii Chao; Wei-Bin Yang (Microelectron. J., 2021)

ThreshNet: An Efficient DenseNet Using Threshold Mechanism to Reduce Connections. - Rui-Yang Ju; Ting-Yu Lin; Jia-Hao Jian; Jen-Shiun Chiang; Wei-Bin Yang (IEEE Access, 2022)

A Programmable Multiple Frequencies Clock Generator With Process and Temperature Compensation Circuit for System on Chip Design. - Wei-Bin Yang; Kuo-Ning Chang; Lu-Chun Yeh (IEEE Syst. J., 2022)

A Programmable DLL-based Delay Chain. - Yu-Wei Huang; Cheng-En Wu; Wei-Bin Yang; Jen-Chieh Liu (ISOCC, 2024)

A Hierarchical Tree-Structured Control Digital Low Drop-out Regulator with Status-Dumping Mechanism. - Jiann-Chyi Rau; Wei-Bin Yang; Yu-Lung Lo; Chin-Yuan Shih; Cheng-Kai Lin; Che-Chia Chuang (ISOCC, 2024)

Texture Classification Network Integrating Adaptive Wavelet Transform. - Su-Xi Yu; Jing-Yuan He; Yi Wang; Yu-Jiao Cai; Jun Yang; Bo Lin; Wei-Bin Yang; Jian Ruan (CoRR, 2024)