A novel dynamic reconfigurable VLSI architecture for H.264 transforms. - Wei Cao 002; Hui Hou; Jinmei Lai 001; Jiarong Tong; Hao Min (APCCAS, 2008)

A high-performance reconfigurable 2-D transform architecture for H.264. - Wei Cao 002; Hui Hou; Jinmei Lai 001; Jiarong Tong; Hao Min (ICECS, 2008)

High-speed and memory-efficient architecture for 2-D 1-Level discrete wavelet transform. - Hui Hou; Wei Cao 002; Fan-jiong Zhang; Jinmei Lai 001; Jiarong Tong (ICECS, 2008)

A high-performance reconfigurable VLSI architecture for vbsme in H.264. - Wei Cao 002; Hui Hou; Jiarong Tong; Jinmei Lai 001; Hao Min (IEEE Trans. Consumer Electron., 2008)

A permutation network for configurable and scalable FFT processors. - Shuai Chen; Jialin Chen; Kanwen Wang; Wei Cao 002; Lingli Wang (ASICON, 2011)

A coarse-grained reconfigurable computing unit. - Kanwen Wang; Shuai Chen; Wei Cao 002; Lingli Wang; Jiarong Tong (ASICON, 2011)

A Reconfigurable Multi-Transform VLSI Architecture Supporting Video Codec Design. - Kanwen Wang; Jialin Chen; Wei Cao 002; Ying Wang 032; Lingli Wang; Jiarong Tong (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A novel structure of dynamic configurable scan chain bypassing unconcerned segments on the fly. - Shengye Wang; Wei Cao 002; Lingli Wang; Na Wang; Ping Tao (ASICON, 2013)

A reconfigurable floating-point FFT architecture. - Chenlu Wu; Wei Cao 002; Xuegong Zhou; Lingli Wang; Fang Wang; Baodi Yuan (ASICON, 2013)

Implementation of high performance hardware architecture of OpenSURF algorithm on FPGA. - Xitian Fan; Chenlu Wu; Wei Cao 002; Xuegong Zhou; Shengye Wang; Lingli Wang (FPT, 2013)

An FPGA-cluster-accelerated match engine for content-based image retrieval. - Chen Liang; Chenlu Wu; Xuegong Zhou; Wei Cao 002; Shengye Wang; Lingli Wang (FPT, 2013)

A hardware implementation of Bag of Words and Simhash for image recognition. - Shengye Wang; Chen Liang; Xuegong Zhou; Wei Cao 002; Chenlu Wu; Xitian Fan; Lingli Wang (FPT, 2013)

Implementation of high performance hardware architecture of face recognition algorithm based on local binary pattern on FPGA. - Yangjie Zhang; Wei Cao 002; Lingli Wang (ASICON, 2015)

DT-CGRA: Dual-track coarse-grained reconfigurable architecture for stream applications. - Xitian Fan; Huimin Li 005; Wei Cao 002; Lingli Wang (FPL, 2016)

A high performance FPGA-based accelerator for large-scale convolutional neural networks. - Huimin Li 005; Xitian Fan; Li Jiao; Wei Cao 002; Xuegong Zhou; Lingli Wang (FPL, 2016)

High performance Deformable Part Model accelerator based on FPGA. - Qi Zhan; Min Gao; Li Jiao; Wei Cao 002; Xuegong Zhou; Lingli Wang (FPT, 2016)

Accelerating low bit-width convolutional neural networks with embedded FPGA. - Li Jiao; Cheng Luo; Wei Cao 002; Xuegong Zhou; Lingli Wang (FPL, 2017)

RNA: An Accurate Residual Network Accelerator for Quantized and Reconstructed Deep Neural Networks. - Cheng Luo; Yuhua Wang; Wei Cao 002; Philip H. W. Leong; Lingli Wang (FPL, 2018)

A Novel Low-Communication Energy-Efficient Reconfigurable CNN Acceleration Architecture. - Di Wu; Jin Chen; Wei Cao 002; Lingli Wang (FPL, 2018)

High Throughput CNN Accelerator Design Based on FPGA. - Liang Xie 009; Xitian Fan; Wei Cao 002; Lingli Wang (FPT, 2018)

Stream Processing Dual-Track CGRA for Object Inference. - Xitian Fan; Di Wu; Wei Cao 002; Wayne Luk; Lingli Wang (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A High Performance FPGA-Based Accelerator Design for End-to-End Speaker Recognition System. - Mingjun Jiao; Yue Li; Pengbo Dang; Wei Cao 002; Lingli Wang (FPT, 2019)

SpWMM: A High-Performance Sparse-Winograd Matrix-Matrix Multiplication Accelerator for CNNs. - Di Wu; Wei Cao 002; Lingli Wang (FPT, 2019)

RNA: An Accurate Residual Network Accelerator for Quantized and Reconstructed Deep Neural Networks. - Cheng Luo; Wei Cao 002; Lingli Wang; Philip H. W. Leong (IEICE Trans. Inf. Syst., 2019)

A Low-Cost Reconfigurable Nonlinear Core for Embedded DNN Applications. - Yue Li; Wei Cao 002; Xuegong Zhou; Lingli Wang (FPT, 2020)

A High-Precision Flexible Symmetry-Aware Architecture for Element-Wise Activation Functions. - Xuan Feng; Yue Li; Yu Qian; Jingbo Gao; Wei Cao 002; Lingli Wang (FPT, 2021)

LETA: A lightweight exchangeable-track accelerator for efficientnet based on FPGA. - Jingbo Gao; Yu Qian; Yihan Hu 003; Xitian Fan; Wai-Shing Luk; Wei Cao 002; Lingli Wang (FPT, 2021)

MRI-based brain tumor segmentation using FPGA-accelerated neural network. - Siyu Xiong; Guoqing Wu 003; Xitian Fan; Xuan Feng; Zhongcheng Huang; Wei Cao 002; Xuegong Zhou; Shijin Ding; Jinhua Yu; Lingli Wang; Zhifeng Shi (BMC Bioinform., 2021)

SWM: A High-Performance Sparse-Winograd Matrix Multiplication CNN Accelerator. - Di Wu; Xitian Fan; Wei Cao 002; Lingli Wang (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Acceleration of Rotated Object Detection on FPGA. - Xitian Fan; Guangwei Xie; Zhongcheng Huang; Wei Cao 002; Lingli Wang (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Unified Accelerator for Attention and Convolution in Inference Based on FPGA. - Tianyang Li; Fan Zhang 044; Xitian Fan; Jianliang Shen; Wei Guo 018; Wei Cao 002 (ISCAS, 2023)

Qubit-Wise Architecture Search Method for Variational Quantum Circuits. - Jialin Chen; Zhiqiang Cai; Ke Xu; Di Wu; Wei Cao 002 (CoRR, 2024)