The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series. - Jonathan Chang; Ming Huang; Jonathan Shoemaker; John Benoit; Szu-Liang Chen; Wei Chen 129; Siufu Chiu; Raghuraman Ganesan; Gloria Leong; Venkata Lukka; Stefan Rusu; Durgesh Srivastava (IEEE J. Solid State Circuits, 2007)

5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family. - Stefan Rusu; Harry Muljono; David Ayers; Simon M. Tam; Wei Chen 129; Aaron Martin; Shenggao Li; Sujal Vora; Raj Varada; Eddie Wang (ISSCC, 2014)

A 22 nm 15-Core Enterprise Xeon® Processor Family. - Stefan Rusu; Harry Muljono; David Ayers; Simon M. Tam; Wei Chen 129; Aaron Martin; Shenggao Li; Sujal Vora; Raj Varada; Eddie Wang (IEEE J. Solid State Circuits, 2015)

SkyLake-SP: A 14nm 28-Core xeon® processor. - Simon M. Tam; Harry Muljono; Min Huang; Sitaraman Iyer; Kalapi Royneogi; Nagmohan Satti; Rizwan Qureshi; Wei Chen 129; Tom Wang; Hubert Hsieh; Sujal Vora; Eddie Wang (ISSCC, 2018)