Variation-aware core-level redundancy scheme for reliable DSP computation in multi-core systems. - Wei-Ching Chu; Huai-Ting Li; Ching-Yao Chou; An-Yeu Andy Wu (SiPS, 2015)

Variation-Aware Reliable Many-Core System Design by Exploiting Inherent Core Redundancy. - Huai-Ting Li; Ching-Yao Chou; Yuan-Ting Hsieh; Wei-Ching Chu; An-Yeu Wu (IEEE Trans. Very Large Scale Integr. Syst., 2017)