Wafer-level 3D integration using hybrid bonding. - Cheng-Ta Ko; Kuan-Neng Chen; Wei-Chung Lo; Chuan-An Cheng; Wen-Chun Huang; Zhi-Cheng Hsiao; Huan-Chun Fu; Yu-Hua Chen (3DIC, 2010)

Cu-based bonding technology for 3D integration applications. - Kuan-Neng Chen; Z. Xu; Fei Liu; Cheng-Ta Ko; Chuan-An Cheng; W. C. Huang; H. L. Lin; C. Cabral; Zhi-Cheng Hsiao; N. Klymko; Hsin-Chia Fu; Y. H. Chen; et al. (3DIC, 2011)

Wafer-level 3D integration with Cu TSV and micro-bump/adhesive hybrid bonding technologies. - Cheng-Ta Ko; Zhi-Cheng Hsiao; Y. J. Chang; Peng-Shu Chen; J. H. Huang; Hsin-Chia Fu; Y. J. Huang; C. W. Chiang; W. L. Tsat; Y. H. Chen; Wei-Chung Lo; Kuan-Neng Chen (3DIC, 2011)

Performance and process characteristic of glass interposer with through-glass-via(TGV). - Chun-Hsien Chien; Hsun Yu; Ching-Kuan Lee; Yu-Min Lin; Ren-Shin Cheng; Chau-Jie Zhan; Peng-Shu Chen; Chang-Chih Liu; Chao-Kai Hsu; Hsiang-Hung Chang; Huan-Chun Fu; Yuan-Chang Lee; et al. (3DIC, 2013)

3D research activities in ITRI. - Wei-Chung Lo (3DIC, 2015)

A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration. - Chih-Sheng Lin; Fu-Cheng Tsai; Jian-Wei Su; Sih-Han Li; Tian-Sheuan Chang; Shyh-Shyuan Sheu; Wei-Chung Lo; Shih-Chieh Chang; Chih-I Wu; Tuo-Hung Hou (A-SSCC, 2021)

16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips. - Jian-Wei Su; Yen-Chi Chou; Ruhui Liu; Ta-Wei Liu; Pei-Jung Lu; Ping-Chun Wu; Yen-Lin Chung; Li-Yang Hung; Jin-Sheng Ren; Tianlong Pan; Sih-Han Li; Shih-Chieh Chang; et al. (ISSCC, 2021)

A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices. - Ping-Chun Wu; Jian-Wei Su; Yen-Lin Chung; Li-Yang Hong; Jin-Sheng Ren; Fu-Chun Chang; Yuan Wu 009; Ho-Yu Chen; Chen-Hsun Lin; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; et al. (ISSCC, 2022)

A 4K-400K Wide Operating-Temperature-Range MRAM Technology with Ultrathin Composite Free Layer and Magnesium Spacer. - Ming-Chun Hong; Yao-Jen Chang; Yu-Chen Hsin; Liang-Ming Liu; Kuan-Ming Chen; Yi-Hui Su; Guan-Long Chen; Shan-Yi Yang; I-Jung Wang; Sk. Ziaur Rahaman; Hsin-Han Lee; Shih-Ching Chiu; et al. (VLSI Technology and Circuits, 2022)

An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging Technology. - Jie Zhang; Wei Lu; Po-Tsang Huang; Sih-Han Li; Tsung-Yi Hung; Shih-Hsien Wu; Ming-Ji Dai; I-Shan Chung; Wen-Chao Chen; Chin-Hung Wang; Shyh-Shyuan Sheu; Hung-Ming Chen; et al. (VLSI Technology and Circuits, 2022)

A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices. - Ping-Chun Wu; Jian-Wei Su; Li-Yang Hong; Jin-Sheng Ren; Chih-Han Chien; Ho-Yu Chen; Chao-En Ke; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; Wei-Chung Lo; Shih-Chieh Chang; et al. (ISSCC, 2023)

U-MRAM: Transistor-Less, High-Speed (10 ns), Low-Voltage (0.6 V), Field-Free Unipolar MRAM for High-Density Data Memory. - Ming-Hung Wu; Ming-Chun Hong; Ching Shih; Yao-Jen Chang; Yu-Chen Hsin; Shih-Ching Chiu; Kuan-Ming Chen; Yi-Hui Su; Chih-Yao Wang; Shan-Yi Yang; Guan-Long Chen; Hsin-Han Lee; et al. (VLSI Technology and Circuits, 2023)

A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips. - Jian-Wei Su; Yen-Chi Chou; Ruhui Liu; Ta-Wei Liu; Pei-Jung Lu; Ping-Chun Wu; Yen-Lin Chung; Li-Yang Hong; Jin-Sheng Ren; Tianlong Pan; Chuan-Jia Jhang; Wei-Hsing Huang; et al. (IEEE J. Solid State Circuits, 2023)

CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device. - Yan-Cheng Guo; Tian-Sheuan Chang; Chih-Sheng Lin; Bo-Cheng Chiou; Chih-Ming Lai; Shyh-Shyuan Sheu; Wei-Chung Lo; Shih-Chieh Chang (ISCAS, 2024)

Empowering Local Differential Privacy: A 5718 TOPS/W Analog PUF-Based In-Memory Encryption Macro for Dynamic Edge Security. - Chih-Sheng Lin; Bo-Cheng Chiou; Yin-Jia Yang; Jian-Wei Su; Kuo-Hua Tseng; Yun-Ting Ho; Chih-Ming Lai; Sih-Han Li; Tian-Sheuan Chang; Shan-Ming Chang; Shyh-Shyuan Sheu; Wei-Chung Lo; et al. (VLSI Technology and Circuits, 2024)

Scalable Embedded Multi-Die Active Bridge (S-EMAB) Chips with Integrated LDOs for Low-Cost Programmable 2.5D/3.5D Packaging Technology. - Wei Lu; Jie Zhang; Yi-Hui Wei; Hsu-Ming Hsiao; Sih-Han Li; Chao-Kai Hsu; Chih-Cheng Hsiao; Feng-Hsiang Lo; Shyh-Shyuan Sheu; Chin-Hung Wang; Wei-Chung Lo; Shih-Chieh Chang; et al. (VLSI Technology and Circuits, 2024)

A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips. - Ping-Chun Wu; Jian-Wei Su; Li-Yang Hong; Jin-Sheng Ren; Chih-Han Chien; Ho-Yu Chen; Chao-En Ke; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; Wei-Chung Lo; Shih-Chieh Chang; et al. (IEEE J. Solid State Circuits, 2024)

8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips. - Jian-Wei Su; Pei-Jung Lu; Ping-Chun Wu; Yen-Chi Chou; Ta-Wei Liu; Yen-Lin Chung; Li-Yang Hung; Jin-Sheng Ren; Wei-Hsing Huang; Chih-Han Chien; Peng-I Mei; Sih-Han Li; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips. - Ping-Chun Wu; Jian-Wei Su; Yen-Lin Chung; Li-Yang Hong; Jin-Sheng Ren; Fu-Chun Chang; Yuan Wu 009; Ho-Yu Chen; Chen-Hsun Lin; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; et al. (IEEE J. Solid State Circuits, 2024)