An ultra-low-voltage LC-VCO with a frequency extension circuit for future 0.5-V clock generation. - Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2011)

A feedback class-C VCO with robust startup condition over PVT variations and enhanced oscillation swing. - Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2011)

A PVT-robust feedback class-C VCO using an oscillation swing enhancement technique. - Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2012)

A 58.1-to-65.0GHz frequency synthesizer with background calibration for millimeter-wave TDD transceivers. - Wei Deng 001; Teerachot Siriburanon; Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2012)

A 0.5-V, 0.05-to-3.2 GHz LC-Based Clock Generator for Substituting Ring Oscillators under Low-Voltage Condition. - Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2012)

A fractional-N harmonic injection-locked frequency synthesizer with 10MHz-6.6GHz quadrature outputs for software-defined radios. - Wei Deng 001; Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2013)

A sub-harmonic injection-locked frequency synthesizer with frequency calibration scheme for use in 60GHz TDD transceivers. - Teerachot Siriburanon; Wei Deng 001; Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2013)

A 13.2% locking-range divide-by-6, 3.1mW, ILFD using even-harmonic-enhanced direct injection technique for millimeter-wave PLLs. - Teerachot Siriburanon; Wei Deng 001; Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2013)

A 0.022mm2 970µW dual-loop injection-locked PLL with -243dB FOM using synthesizable all-digital PVT calibration circuits. - Wei Deng 001; Ahmed Musa; Teerachot Siriburanon; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2013)

A 20 GHz Push-Push Voltage-Controlled Oscillator Using Second-Harmonic Peaking Technique for a 60 GHz Frequency Synthesizer. - Teerachot Siriburanon; Takahiro Sato; Ahmed Musa; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2013)

Class-C VCO With Amplitude Feedback Loop for Robust Start-Up and Enhanced Oscillation Swing. - Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2013)

A Sub-Harmonic Injection-Locked Quadrature Frequency Synthesizer With Frequency Calibration Scheme for Millimeter-Wave TDD Transceivers. - Wei Deng 001; Teerachot Siriburanon; Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2013)

A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation. - Wei Deng 001; Ahmed Musa; Teerachot Siriburanon; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2014)

A swing-enhanced current-reuse class-C VCO with dynamic bias control circuits. - Teerachot Siriburanon; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2014)

A 0.011 mm2 PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI. - Aravind Tharayil Narayanan; Wei Deng 001; Dongsheng Yang 002; Rui Wu 001; Kenichi Okada 001; Akira Matsuzawa (A-SSCC, 2014)

A 0.015-mm2 60-GHz reconfigurable wake-up receiver by reusing multi-stage LNAs. - Rui Wu 001; Qinghong Bu; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (A-SSCC, 2014)

A pulse-driven LC-VCO with a figure-of-merit of -192dBc/Hz. - Aravind Tharayil Narayanan; Kento Kimura; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2014)

15.1 A 0.0066mm2 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique. - Wei Deng 001; Dongsheng Yang 002; Tomohiro Ueno; Teerachot Siriburanon; Satoshi Kondo; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2014)

A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios. - Wei Deng 001; Shoichi Hara; Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2014)

A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration. - Ahmed Musa; Wei Deng 001; Teerachot Siriburanon; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2014)

A tail-current modulated VCO with adaptive-bias scheme. - Aravind Tharayil Narayanan; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2015)

A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection. - Teerachot Siriburanon; Tomohiro Ueno; Kento Kimura; Satoshi Kondo; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2015)

An HDL-synthesized gated-edge-injection PLL with a current output DAC. - Dongsheng Yang 002; Wei Deng 001; Tomohiro Ueno; Teerachot Siriburanon; Satoshi Kondo; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2015)

A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of -246dB. - Aravind Tharayil Narayanan; Makihiko Katsuragi; Kento Kimura; Satoshi Kondo; Korkut Kaan Tokgoz; Kengo Nakata; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2015)

A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular. - Teerachot Siriburanon; Hanli Liu; Kengo Nakata; Wei Deng 001; Ju Ho Son; Dae Young Lee; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2015)

14.1 A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique. - Wei Deng 001; Dongsheng Yang 002; Aravind Tharayil Narayanan; Kengo Nakata; Teerachot Siriburanon; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2015)

25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture. - Teerachot Siriburanon; Satoshi Kondo; Kento Kimura; Tomohiro Ueno; Satoshi Kawashima; Tohru Kaneko; Wei Deng 001; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2015)

A fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI. - Dongsheng Yang 002; Wei Deng 001; Aravind Tharayil Narayanan; Rui Wu 001; Bangan Liu; Kenichi Okada 001; Akira Matsuzawa (IEICE Electron. Express, 2015)

A Constant-Current-Controlled Class-C Voltage-Controlled Oscillator using Self-Adjusting Replica Bias Circuit. - Teerachot Siriburanon; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2015)

A 60-GHz CMOS Transmitter with Gain-Enhanced On-Chip Antenna for Short-Range Wireless Interconnections. - Rui Wu 001; Wei Deng 001; Shinji Sato; Takuichi Hirano; Ning Li 009; Takeshi Inoue; Hitoshi Sakane; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2015)

A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique. - Wei Deng 001; Dongsheng Yang 002; Tomohiro Ueno; Teerachot Siriburanon; Satoshi Kondo; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2015)

An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection. - Dongsheng Yang 002; Wei Deng 001; Aravind Tharayil Narayanan; Kengo Nakata; Teerachot Siriburanon; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2016)

An LC-DCO based synthesizable injection-locked PLL with an FoM of -250.3dB. - Dongsheng Yang 002; Wei Deng 001; Bangan Liu; Teerachot Siriburanon; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2016)

A 0.0055mm2 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI. - Dongsheng Yang 002; Tomohiro Ueno; Wei Deng 001; Yuki Terashima; Kengo Nakata; Aravind Tharayil Narayanan; Rui Wu 001; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2016)

A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB. - Aravind Tharayil Narayanan; Makihiko Katsuragi; Kento Kimura; Satoshi Kondo; Korkut Kaan Tokgoz; Kengo Nakata; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2016)

A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad. - Teerachot Siriburanon; Satoshi Kondo; Makihiko Katsuragi; Hanli Liu; Kento Kimura; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2016)

A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture. - Teerachot Siriburanon; Satoshi Kondo; Kento Kimura; Tomohiro Ueno; Satoshi Kawashima; Tohru Kaneko; Wei Deng 001; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2016)

An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation. - Dongsheng Yang 002; Wei Deng 001; Bangan Liu; Aravind Tharayil Narayanan; Teerachot Siriburanon; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2017)

A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI. - Aravind Tharayil Narayanan; Wei Deng 001; Dongsheng Yang 002; Rui Wu 001; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2017)

A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique. - Bangan Liu; Huy Cu Ngo; Kengo Nakata; Wei Deng 001; Yuncheng Zhang; Junjun Qiu; Toru Yoshioka; Jun Emmei; Haosheng Zhang; Jian Pang; Aravind Tharayil Narayanan; Dongsheng Yang 002; et al. (CICC, 2018)

A 0.85mm2 BLE Transceiver with Embedded T/R Switch, 2.6mW Fully-Passive Harmonic Suppressed Transmitter and 2.3mW Hybrid-Loop Receiver. - Zheng Sun 001; Hanli Liu; Dexian Tang; Hongye Huang; Tohru Kaneko; Rui Wu 001; Wei Deng 001; Kenichi Okada 001 (ESSCIRC, 2018)

An ADPLL-centric bluetooth low-energy transceiver with 2.3mW interference-tolerant hybrid-loop receiver and 2.9mW single-point polar transmitter in 65nm CMOS. - Hanli Liu; Zheng Sun 001; Dexian Tang; Hongye Huang; Tohru Kaneko; Wei Deng 001; Rui Wu 001; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2018)

A 0.98mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of -246dB for IoT applications in 65nm CMOS. - Hanli Liu; Dexian Tang; Zheng Sun 001; Wei Deng 001; Huy Cu Ngo; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2018)

A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Mobile Communications in 65nm CMOS. - Hanli Liu; Teerachot Siriburanon; Kengo Nakata; Wei Deng 001; Ju Ho Son; Dae Young Lee; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2018)

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS. - Hanli Liu; Zheng Sun 001; Dexian Tang; Hongye Huang; Tohru Kaneko; Zhijie Chen; Wei Deng 001; Rui Wu 001; Kenichi Okada 001 (IEEE J. Solid State Circuits, 2018)

A Sub-mW Fractional-N ADPLL With FOM of -246 dB for IoT Applications. - Hanli Liu; Dexian Tang; Zheng Sun 001; Wei Deng 001; Huy Cu Ngo; Kenichi Okada 001 (IEEE J. Solid State Circuits, 2018)

An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration. - Bangan Liu; Yuncheng Zhang; Junjun Qiu; Wei Deng 001; Zule Xu; Haosheng Zhang; Jian Pang; Yun Wang 008; Rui Wu 001; Teruki Someya; Atsushi Shirane; Kenichi Okada 001 (CICC, 2019)

A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS. - Hanli Liu; Zheng Sun 001; Hongye Huang; Wei Deng 001; Teerachot Siriburanon; Jian Pang; Yun Wang 008; Rui Wu 001; Teruki Someya; Atsushi Shirane; Kenichi Okada 001 (ISSCC, 2019)

A 265- $ mu$ W Fractional- ${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS. - Hanli Liu; Atsushi Shirane; Kenichi Okada 001; Zheng Sun 001; Hongye Huang; Wei Deng 001; Teerachot Siriburanon; Jian Pang; Yun Wang 008; Rui Wu 001; Teruki Someya (IEEE J. Solid State Circuits, 2019)

A 44-52 GHz Reflection-type Phase Shifter with 1.4° Phase Resolution in 28nm CMOS Process. - Shengnan Dong; Zipeng Chen; Haikun Jia; Wei Deng 001; Baoyong Chi (ICTA, 2020)

A 53.1-to-64.5 GHz In-Phase Coupled Quadrature Injection-Locked Oscillator with Transformer-Based I/Q-Phase Differential Injection Scheme. - Chenggang Li; Rui Wu 001; Haikun Jia; Wei Deng 001; Baoyong Chi (ICTA, 2020)

A 35-GHz TX and RX CMOS Front-Ends for Ka-Band FMCW Phased-Array Radar Transceivers. - Wei Deng 001; Rui Wu 001; Zhijie Chen; Manlai Ding; Baoyong Chi (ISCAS, 2020)

A FoM of -191 dB, 4.4-GHz LC-VCO Integrating an 8-Shaped Inductor with an Orthogonal-Coupled Tail-Filtering Inductor. - Yaqian Sun; Wei Deng 001; Baoyong Chi (ISCAS, 2020)

An Energy-Efficient 10-Gb/s CMOS Millimeter-Wave Transceiver With Direct-Modulation Digital Transmitter and I/Q Phase-Coupled Frequency Synthesizer. - Wei Deng 001; Zheng Song 002; Ruichang Ma; Jianfu Lin; Yutian Li; Jialiang Ye; Shangcheng Kong; Sanming Hu; Haikun Jia; Baoyong Chi (IEEE J. Solid State Circuits, 2020)

A CMOS 76-81-GHz 2-TX 3-RX FMCW Radar Transceiver Based on Mixed-Mode PLL Chirp Generator. - Taikun Ma; Wei Deng 001; Zipeng Chen; Jianxi Wu; Wei Zheng; Shufu Wang; Nan Qi; Yibo Liu; Baoyong Chi (IEEE J. Solid State Circuits, 2020)

A U-Band PLL Using Implicit Distributed Resonators for Sub-THz Wireless Transceivers in 40 nm CMOS. - Zipeng Chen; Wei Deng 001; Haikun Jia; Yibo Liu; Jianxi Wu; Pingda Guan; Jinyu Zhu; Luhong Mao; Zhihua Wang 001; Baoyong Chi (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 77-GHz Mixed-Mode FMCW Generator Based on a Vernier TDC With Dual Rising-Edge Fractional-Phase Detector. - Jianxi Wu; Wei Deng 001; Zipeng Chen; Wei Zheng; Yibo Liu; Shufu Wang; Nan Qi; Baoyong Chi (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A 35-GHz TX and RX Front End With High TX Output Power for Ka-Band FMCW Phased-Array Radar Transceivers in CMOS Technology. - Wei Deng 001; Rui Wu 001; Zhijie Chen; Manlai Ding; Haikun Jia; Baoyong Chi (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A Highly Integrated Energy-efficient CMOS Millimeter-wave Transceiver with Direct-modulation Digital Transmitter, Quadrature Phased-coupled Frequency Synthesizer and Substrate-Integrated Waveguide E-shaped Patch Antenna. - Wei Deng 001; Zheng Song 002; Ruichang Ma; Haikun Jia; Baoyong Chi (ASP-DAC, 2021)

A 33.5-37.5 GHz 4-Element Phased-Array Transceiver Front-End with High-Accuracy Low-Variation 6-bit Resolution 360° Phase Shift and 0 31.5 dB Gain Control in 65 nm CMOS. - Pingda Guan; Haikun Jia; Wei Deng 001; Zhihua Wang 001; Baoyong Chi (A-SSCC, 2021)

A 24-30GHz 4-Element Phased Array Transceiver with Low Insertion Loss Compact T/R Switch and Bidirectional Phase Shifter in 65 nm CMOS Technology. - Xiangrong Huang; Haikun Jia; Shengnan Dong; Wei Deng 001; Zhihua Wang 001; Baoyong Chi (A-SSCC, 2021)

An 8.2-to-21.5 GHz Dual-Core Quad-Mode Orthogonal-Coupled VCO with Concurrently Dual-Output using Parallel 8-Shaped Resonator. - Wei Deng 001; Haikun Jia; Rui Wu 001; Shiyan Sun; Chenggang Li; Zhihua Wang 001; Baoyong Chi (CICC, 2021)

An Ultra-Compact 16-to-45 GHz Power Amplifier within A Single Inductor Footprint Using Folded Transformer Technique. - Pingda Guan; Haikun Jia; Wei Deng 001; Zhihua Wang 001; Baoyong Chi (CICC, 2021)

Optimization methods for high inductance-density inductors for high speed integrated circuits. - Ziyue Dang; Haikun Jia; Wei Deng 001; Zhihua Wang 001; Baoyong Chi (ICTA, 2021)

A C-band FMCW Radar Transmitter with a 22 dBm Output Power Series-stacking CMCD PA for Long-distance Detection in 180-nm CMOS Technology. - Xiangrong Huang; Wei Deng 001; Haikun Jia; Yuhui Wei; Zhihua Wang 001; Baoyong Chi (ICTA, 2021)

A 60GHz 186.5dBc/Hz FoM Quad-Core Fundamental VCO Using Circular Triple-Coupled Transformer with No Mode Ambiguity in 65nm CMOS. - Haikun Jia; Wei Deng 001; Pingda Guan; Zhihua Wang 001; Baoyong Chi (ISSCC, 2021)

A 11.1-to-14.2 GHz Self-adapted Two-point Modulation Dual-path Type-II Digital PLL Concurrently Achieving 124.7-MHz/μs Chirp Rate and 2.27-GHz Bandwidth. - Wei Deng 001; Zipeng Chen; Haikun Jia; Shiyan Sun; Guopei Chen; Zhihua Wang 001; Baoyong Chi (VLSI Circuits, 2021)

A 122-168GHz Radar/Communication Fusion-Mode Transceiver with 30GHz Chirp Bandwidth, 13dBm Psat, and 8.3dBm OP1dB in 28nm CMOS. - Zipeng Chen; Wei Deng 001; Haikun Jia; Pingda Guan; Taikun Ma; Shiyan Sun; Xiangrong Huang; Guopei Chen; Ruichang Ma; Shengnan Dong; Luqiang Duan; Zhihua Wang 001; et al. (VLSI Circuits, 2021)

A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration. - Bangan Liu; Yuncheng Zhang; Junjun Qiu; Huy Cu Ngo; Wei Deng 001; Kengo Nakata; Toru Yoshioka; Jun Emmei; Jian Pang; Aravind Tharayil Narayanan; Haosheng Zhang; Teruki Someya; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 0.85mm2 BLE Transceiver Using an On-Chip Harmonic-Suppressed RFIO Circuitry With T/R Switch. - Zheng Sun 001; Hanli Liu; Hongye Huang; Dexian Tang; Dingxin Xu; Tohru Kaneko; Zheng Li 021; Jian Pang; Rui Wu 001; Wei Deng 001; Atsushi Shirane; Kenichi Okada 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 76-81 GHz FMCW 2TX/3RX Radar Transceiver with Integrated Mixed-Mode PLL and Series-Fed Patch Antenna Array. - Taikun Ma; Wei Deng 001; Haikun Jia; Yejun He; Baoyong Chi (ASP-DAC, 2022)

A 12.5-to-15.4GHz, -118.9dBc/Hz PN at 1MHz offset, and 191.0dBc/Hz FoM VCO with Common-Mode Resonance Expansion and Simultaneous Differential 2ND-Harmonic Output using a Single Three-Coil Transformer in 65nm CMOS. - Ruichang Ma; Haikun Jia; Wei Deng 001; Zhihua Wang 001; Baoyong Chi (CICC, 2022)

A 4.7GHz Synchronized-Multi-Reference PLL with In-Band Phase Noise Lower than Reference Phase Noise +20logNdiv. - Hongzhuo Liu; Wei Deng 001; Haikun Jia; Shiyan Sun; Qixiu Wu; Jiajie Tang; Zhihua Wang 001; Baoyong Chi (ESSCIRC, 2022)

A 22.8 GHz to 32.8 GHz Compact Power Amplifier with a 15 dBm Output P1dB and 36.5% Peak PAE in 65-nm CMOS. - Huabing Liao; Haikun Jia; Xiangrong Huang; Bao Shi; Wei Deng 001; Baoyong Chi; Zhihua Wang 001 (ICTA, 2022)

A Highly Linearized Ka-band Heterodyne Receiver using a Folded Class-AB Inductive Peaking Mixer and Magnetic-Self-Cancellation-Transformer-Based IF Amplifiers. - Qixiu Wu; Wei Deng 001; Haikun Jia; Rui Wu 001; Fuyuan Zhao; Baoyong Chi (ISCAS, 2022)

A 53.6-to-60.2GHz Many-Core Fundamental Oscillator With Scalable Mesh Topology Achieving -136.0dBc/Hz Phase Noise at 10MHz Offset and 190.3dBc/Hz Peak FoM in 65nm CMOS. - Haikun Jia; Ruichang Ma; Wei Deng 001; Zhihua Wang 001; Baoyong Chi (ISSCC, 2022)

A Self-Adapted Two-Point Modulation Type-II Digital PLL for Fast Chirp Rate and Wide Chirp-Bandwidth FMCW Signal Generation. - Wei Deng 001; Zipeng Chen; Haikun Jia; Angxiao Yan; Shiyan Sun; Guopei Chen; Zhihua Wang 001; Baoyong Chi (IEEE J. Solid State Circuits, 2022)

A 4.4-GHz 193.2-dB FoM 8-Shaped-Inductor Based LC-VCO Using Orthogonal-Coupled Triple-Coil Transformer. - Yaqian Sun; Wei Deng 001; Haikun Jia; Zhihua Wang 001; Baoyong Chi (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Fully Integrated Bit-to-Bit 24/48Gb/s QPSK/16-QAM D-Band Transceiver with Mixed-Signal Baseband in 28nm CMOS Technology. - Pingda Guan; Haikun Jia; Wei Deng 001; Ruichang Ma; Mingxing Deng; Jiamin Xue; Angxiao Yan; Shiyan Sun; Zhihua Wang 001; Baoyong Chi (A-SSCC, 2023)

A Compact E-Band Load-Modulation Balanced Power Amplifier Using Coupled Transmission-Line Output Network Achieving 22.1-dBm Psat and 34.9%/12.2% Efficiency at Psat/6-dB PBO. - Xiangrong Huang; Haikun Jia; Wei Deng 001; Zhihua Wang 001; Baoyong Chi (A-SSCC, 2023)

A 4-Element 4-Beam Ka-Band Phased-Array Receiver Using Mesh Topology in 65 nm CMOS. - Xiangrong Huang; Haikun Jia; Wei Deng 001; Chuanming Zhu; Zhihua Wang 001; Xuzhi Liu; Zhiming Chen 001; Baoyong Chi (A-SSCC, 2023)

A 27-to-31.6 GHz 8-Element Phased-Array Transmitter Front-End with Inter-Element-Interference Cancellation Scheme in 65 nm CMOS. - Dongze Li; Wei Deng 001; Xintao Li; Ruiheng Qiu; Haikun Jia; Xiangrong Huang; Ziyuan Guo; Baoyong Chi (A-SSCC, 2023)

A 26.9-GHz 4-Element Code-Domain Hybrid Beamforming Phased-Array Receiver. - Ziyi Lin; Haikun Jia; Chuanming Zhu; Wei Deng 001; Huabing Liao; Bao Shi; Lujie Hao; Xiangrong Huang; Baoyong Chi (A-SSCC, 2023)

IEEE ASSCC 2023/ Session 10/ Paper 10.5. - Ruichang Ma; Haikun Jia; Hongzhuo Liu; Wei Deng 001; Zhihua Wang 001; Baoyong Chi (A-SSCC, 2023)

A Transient Enhancement Digital LDO with Adaptive Ripple Cancelation Based on Optimal Compensation Period Approximation. - Angxiao Yan; Wei Deng 001; Haikun Jia; Shiwei Zhang; Baoyong Chi (A-SSCC, 2023)

A 25.0-to-35.9GHz Dual-Layer Quad-Core Dual-Mode VCO with 189.1dBc/Hz FoM and 200.2dBc/Hz FoMT at 1MHz Offset in 65nm CMOS. - Pingda Guan; Haikun Jia; Wei Deng 001; Ruichang Ma; Huabing Liao; Zhihua Wang 001; Baoyong Chi (CICC, 2023)

A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS. - Shiwei Zhang; Wei Deng 001; Haikun Jia; Hongzhuo Liu; Shiyan Sun; Pingda Guan; Baoyong Chi (CICC, 2023)

Transceiver SoC for Wireless Indoor Sensing Data-fusion. - Bufan Zhu; Wei Deng 001; Ziying Huang; Haikun Jia; Haiyang Jia; Angxiao Yan; Yumeng Yang; Junfeng Liu; Yu Fu; Shiyan Sun; Chao Tang; Taikun Ma; et al. (CICC, 2023)

A 37-to-41.8 GHz Double-Gm-Boosting LNA with 2.9-dB NFmin Using Quadruple-Coupling Transformer for Phased-Array Transceivers. - Dongze Li; Wei Deng 001; Haikun Jia; Ruiheng Qiu; Xintao Li; Ziyuan Guo; Baoyong Chi (ESSCIRC, 2023)

A 4.8-GHz Time-Interleaved Multi-Reference PLL with 16.1-fs Jitter. - Hongzhuo Liu; Wei Deng 001; Haikun Jia; Shiwei Zhang; Shiyan Sun; Baoyong Chi (ESSCIRC, 2023)

INVITED PAPER: A 312.5Mbps-32Gbps JESD204C Wireline Transceiver Back-Compatible with JESD204B in 28nm CMOS. - Shijie Li; Ruichang Ma; Mingxing Deng; Jiamin Xue; Wei Deng 001; Baoyong Chi; Haikun Jia (ICTA, 2023)

A 6.5-to-8GHz IEEE 802.15.4z-compliant All-Digital UWB Transmitter with Integrated Fast-Settling Master-Slave Regulator. - Ziying Huang; Wei Deng 001; Haikun Jia; Bufan Zhu; Angxiao Yan; Baoyong Chi (ISCAS, 2023)

An 11.5-to-14.3GHz 192.8dBc/Hz FoM at 1MHz Offset Dual-Core Enhanced Class-F VCO with Common-Mode-Noise Self-Cancellation and Isolation Technique. - Qixiu Wu; Wei Deng 001; Haikun Jia; Hongzhuo Liu; Shiwei Zhang; Zhihua Wang 001; Baoyong Chi (ISSCC, 2023)

A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1st/2nd-Order DTC INL Calibration. - Yumeng Yang; Wei Deng 001; Angxiao Yan; Haikun Jia; Junlong Gong; Zhihua Wang 001; Baoyong Chi (ISSCC, 2023)

An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope. - Angxiao Yan; Wei Deng 001; Haikun Jia; Shiyan Sun; Chao Tang; Bufan Zhu; Yu Fu; Hongzhuo Liu; Baoyong Chi (VLSI Technology and Circuits, 2023)

A D-Band Joint Radar-Communication CMOS Transceiver. - Wei Deng 001; Zipeng Chen; Haikun Jia; Pingda Guan; Taikun Ma; Angxiao Yan; Shiyan Sun; Xiangrong Huang; Guopei Chen; Ruichang Ma; Shengnan Dong; Luqiang Duan; et al. (IEEE J. Solid State Circuits, 2023)

A Low-Phase-Noise Quad-Core Millimeter-Wave Fundamental VCO Using Circular Triple-Coupled Transformer in 65-nm CMOS. - Haikun Jia; Pingda Guan; Wei Deng 001; Zhihua Wang 001; Baoyong Chi (IEEE J. Solid State Circuits, 2023)

A Compact and Low Phase Noise Square-Geometry Quad-Core Class-F VCO Using Parallel Inductor-Sharing Technique. - Yaqian Sun; Wei Deng 001; Haikun Jia; Yejun He; Zhihua Wang 001; Baoyong Chi (IEEE J. Solid State Circuits, 2023)

A 24-30-GHz Four-Element Phased Array Transceiver With Low Insertion Loss Compact T/R Switch and Bidirectional Phase Shifter for 5G Communication. - Xiangrong Huang; Haikun Jia; Shengnan Dong; Wei Deng 001; Zhihua Wang 001; Baoyong Chi (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A Fully-Connected Time-Modulated Phased-Array Transmitter Featuring Physical Security Directional Link and Multi-Beam PAPR Reduction. - Xiangrong Huang; Haikun Jia; Wei Deng 001; Chuanming Zhu; Ruiyang Jiang; Xintao Li; Zhihua Wang; Baoyong Chi (A-SSCC, 2024)

A 130-to-170 GHz Reconfigurable Heterodyne/Homodyne Transceiver Achieving 20.5-dBm Psat for Emerging Integrated Wireless Access and Backhaul Networks. - Qixiu Wu; Wei Deng 001; Ziyuan Guo; Haikun Jia; Taikun Ma; Qiuyu Peng; Chang Liu; Baoyong Chi (A-SSCC, 2024)

A 3-to-40 GHz 64QAM/256QAM/4096QAM Zero-IF CMOS Transceiver Chipset for Millimeter-wave Software-defined Radios. - Wenjing Ye; Wei Deng 001; Haikun Jia; Jingling Zhang; Linjun Gu; Fuyuan Zhao; Ruichen Wan; Baoyong Chi (A-SSCC, 2024)

A 48MHz Temperature Compensated Crystal Oscillator Utilizing Time-Domain Accuracy Boosting Techniques Achieving ±1.4ppm Frequency Stability from -55°C to 115°C. - Junyang Yin; Wei Deng 001; Haikun Jia; Minshuo Wang; Baoyong Chi (A-SSCC, 2024)

A 194.9dBc/Hz FoM and 6.8-to-11.6GHz Quad-Core Dual-Mode Class-F VCO Featuring Wideband Flicker Noise Suppression. - Huanyu Ge; Haikun Jia; Wei Deng 001; Ruichang Ma; Baoyong Chi (CICC, 2024)

An 11.1-to-14.9GHz Digital-Integral Hybrid-Proportional Fractional-N PLL with an LC DTC Achieving 0.52μs Locking Time and 41.3f5 Jitter. - Hongzhuo Liu; Wei Deng 001; Haikun Jia; Baoyong Chi (CICC, 2024)

INVITED PAPER: A 21.5-to-37 GHz Series Doherty CMOS Power Amplifier with Distributed Multi-step Impedance Inverting Network Achieving 28.2%/23.2%/13.2% Peak/OP1dB/6dBPBO PAEs. - Xinyu Jiang; Wei Deng 001; Junlong Gong; Haikun Jia; Baoyong Chi (ICTA, 2024)

A 24.3-to-44.8 GHz Reconfigurable Dual-Band T/R Front-End with An Implicit Switch-based Antenna Interface Supporting 600MSym/s 64QAM. - Junlong Gong; Wei Deng 001; Fuyuan Zhao; Haikun Jia; Wenjing Ye; Ruichen Wan; Baoyong Chi (ISCAS, 2024)

19.5 A 13.7-to-41.5GHz 214.1dBc/Hz FoMT Quad-Core Quad-Mode VCO Using an Oscillation-Mode-Splitting Technique. - Huanyu Ge; Haikun Jia; Wei Deng 001; Ruichang Ma; Zhihua Wang 001; Baoyong Chi (ISSCC, 2024)

A 132-to-163 GHz 4TX/4RX Distributed MIMO FMCW Radar Transceiver with Real-Time Reference-Clock Synchronization Enabling Cooperative Coherent Multistatic Imaging System. - Ruichen Wan; Wei Deng 001; Qixiu Wu; Haikun Jia; W. Rui; Angxiao Yan; Haowen Cai; Sanming Hu; Zhihua Wang 001; Baoyong Chi (VLSI Technology and Circuits, 2024)

A Low-Phase-Noise VCO With Common-Mode Resonance Expansion and Intrinsic Differential 2nd-Harmonic Output Based on a Single Three-Coil Transformer. - Ziyi Lin; Haikun Jia; Ruichang Ma; Wei Deng 001; Zhihua Wang 001; Baoyong Chi (IEEE J. Solid State Circuits, 2024)

A Band-Shifting Millimeter-Wave T/R Front-End Using Inductance-Mutation Transformer Technique for Multiband Phased-Array Transceivers. - Fuyuan Zhao; Wei Deng 001; Haikun Jia; Wenjing Ye; Ruichen Wan; Zhihua Wang 001; Baoyong Chi (IEEE J. Solid State Circuits, 2024)

Correction to "A 4.4-GHz 193.2-dB FoM 8-Shaped-Inductor-Based LC-VCO Using Orthogonal-Coupled Triple-Coil Transformer". - Yaqian Sun; Wei Deng 001; Haikun Jia; Zhihua Wang 001; Baoyong Chi (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Multireference PLL: Theory and Implementation. - Hongzhuo Liu; Wei Deng 001; Haikun Jia; Shiwei Zhang; Shiyan Sun; Zhihua Wang 001; Baoyong Chi (IEEE J. Solid State Circuits, 2024)

An Enhanced Class-F Dual-Core VCO With Common-Mode-Noise Self-Cancellation and Isolation Technique. - Qixiu Wu; Wei Deng 001; Yaqian Sun; Haikun Jia; Hongzhuo Liu; Shiwei Zhang; Zhihua Wang 001; Baoyong Chi (IEEE J. Solid State Circuits, 2024)

28 GHz Compact LNAs With 1.9 dB Minimum NF Using Folded Three-Coil Transformer and Dual-Feedforward Techniques for Phased Array Systems. - Xiangrong Huang; Haikun Jia; Wei Deng 001; Zhihua Wang 001; Baoyong Chi; Ziqiang Wang (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A Fully Integrated QPSK/16-QAM D-Band CMOS Transceiver With Mixed-Signal Baseband Circuitry Realizing Digital Interfaces. - Pingda Guan; Ruichang Ma; Haikun Jia; Wei Deng 001; Mingxing Deng; Jiamin Xue; Angxiao Yan; Shiyan Sun; Qiuyu Peng; Teerachot Siriburanon; Robert Bogdan Staszewski; Zhihua Wang 001; et al. (IEEE J. Solid State Circuits, 2024)

A Compact E-Band Load-Modulation Balanced Power Amplifier in 65-nm CMOS. - Xiangrong Huang; Haikun Jia; Wei Deng 001; Zhihua Wang 001; Baoyong Chi (IEEE J. Solid State Circuits, 2024)

A 22.0-to-28.4GHz 192.2dBc/Hz FoM and 206.2dBc/Hz FoMA Dual-Core VCO Using Circular-Inverse-Class-F Topology Under Standard Supply Voltage in 65nm CMOS Process. - Huanyu Ge; Haikun Jia; Wei Deng 001; Baoyong Chi (CICC, 2025)

A 22-to-32 GHz 4-Beam 32-Element Polarization Reconfigurable Fully-Connected Fully-Bidirectional MIMO Transceiver for Emerging Space-Air-Ground-Sea Integrated Network. - Junlong Gong; Wei Deng 001; Shulin Yao; Haikun Jia; Xinyu Jiang; Xiangyu Nie; Dongfang Li; Hongliang Wu; Chuanming Zhu; Xiangrong Huang; Baoyong Chi (CICC, 2025)

A 104-to-132 GHz 16-way Power Amplifier Using Enhanced Magnetic Coupling Cavity Achieving 21.2 dBm Output Power in 28nm Bulk CMOS. - Ziyuan Guo; Wei Deng 001; Weiqi Zheng; Haikun Jia; Hongliang Wu; Qiuyu Peng; Fuyuan Zhao; Junyang Yin; Dongze Li; Baoyong Chi (CICC, 2025)

A 0.18-µs-Locking-Time Fractional-N PLL with Stochastic Gradient Descent Tuning Curve Fitting, Initial Phase Error Zeroing, and Random DSM Achieving 44.4-fs Jitter at Near-Integer Channel. - Hongzhuo Liu; Wei Deng 001; Haikun Jia; Baoyong Chi (CICC, 2025)

A 112Gb/s Analog-MUX-based PAM-4 Transmitter with Inherent 2-tap FFE in 65nm CMOS. - Ziyi Lin; Haikun Jia; Shitu He; Wei Deng 001; Chang Liu; Ruiheng Qiu; Chen Wang; Baoyong Chi (ISCAS, 2025)

A Total Noise Power Based Digital Calibration Method for Continuous-Time Delta-Sigma Modulators. - Zhuojian Yao; Haikun Jia; Lilan Yu; Junfeng Liu; Yu Fu; Wei Deng 001; Baoyong Chi (ISCAS, 2025)

19.9 An 11-to-16.4GHz, 3.4GHz/µs-Slope, 5.32GHz-Chirp-Bandwidth, 0.043%-RMS-Frequency-Error FMCW Digital PLL with Posterior-Segment DPD Featuring 5-Chirp-Cycle Convergence Time. - Angxiao Yan; Wei Deng 001; Haikun Jia; Yumeng Yang; Chao Tang; Shiyan Sun; Zhihua Wang 001; Baoyong Chi (ISSCC, 2025)

A Transformer-Based Series-Resonance CMOS VCO. - Shiwei Zhang; Wei Deng 001; Haikun Jia; Hongzhuo Liu; Shiyan Sun; Pingda Guan; Zhihua Wang 001; Baoyong Chi (IEEE J. Solid State Circuits, 2025)

An Ultra-Low-Jitter Fast-Hopping Fractional-N PLL With LC DTC and Hybrid-Proportional Paths. - Hongzhuo Liu; Wei Deng 001; Haikun Jia; Zhihua Wang 001; Baoyong Chi (IEEE J. Solid State Circuits, 2025)

A Digital-Intensive 1TX/2RX IEEE 802.15.4/4z-Compliant Joint-Radar-Communication-Location Transceiver SoC. - Bufan Zhu; Wei Deng 001; Ziying Huang; Haikun Jia; Haiyang Jia; Angxiao Yan; Yumeng Yang; Junfeng Liu; Yu Fu; Shiyan Sun; Chao Tang; Lixue Kuang; et al. (IEEE J. Solid State Circuits, 2025)

A Multi-Core Series-Resonance CMOS Oscillator. - Shiwei Zhang; Wei Deng 001; Haikun Jia; Zhihua Wang 001; Baoyong Chi (IEEE J. Solid State Circuits, 2025)

A 26-Gb/s 140-GHz OOK CMOS Transmitter and Receiver Chipset for High-Speed Wireless and Dielectric Waveguide Communication. - Qiuyu Peng; Haikun Jia; Ran Fang; Pingda Guan; Mingxing Deng; Jiamin Xue; Wei Deng 001; Xin Liang; Baoyong Chi (IEEE J. Solid State Circuits, 2025)