A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed. - Zhibo Wang 004; Yongpan Liu; Albert Lee; Fang Su; Chieh-Pu Lo; Zhe Yuan; Jinyang Li 002; Chien-Chen Lin; Wei-Hao Chen; Hsiao-Yun Chiu; Wei-En Lin; Ya-Chin King; et al. (IEEE J. Solid State Circuits, 2017)

A Reconfigurable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source With <6×10-6 Native Bit Error Rate. - Yachun Pang; Bin Gao 006; Dong Wu; Shengyu Yi; Qi Liu 010; Wei-Hao Chen; Ting-Wei Chang; Wei-En Lin; Xiaoyu Sun 001; Shimeng Yu; He Qian; Meng-Fan Chang; et al. (ISSCC, 2019)

A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors. - Cheng-Xin Xue; Wei-Hao Chen; Je-Syu Liu; Jia-Fang Li; Wei-Yu Lin; Wei-En Lin; Jing-Hong Wang; Wei-Chen Wei; Ting-Wei Chang; Tung-Cheng Chang; Tsung-Yuan Huang; Hui-Yao Kao; et al. (ISSCC, 2019)

Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors. - Cheng-Xin Xue; Ting-Wei Chang; Tung-Cheng Chang; Hui-Yao Kao; Yen-Cheng Chiu; Chun-Ying Lee; Ya-Chin King; Chrong Jung Lin; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Wei-Hao Chen; et al. (IEEE J. Solid State Circuits, 2020)

Plantwide optimization coupled with column sequencing and stacking using a process simulator automation server. - Yuan-Wei Ni; Wei-En Lin; Wei-Ting Tang; Jeffrey D. Ward (Comput. Chem. Eng., 2021)

A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source. - Bohan Lin; Yachuan Pang; Bin Gao 006; Jianshi Tang; Dong Wu; Ting-Wei Chang; Wei-En Lin; Xiaoyu Sun 001; Shimeng Yu; Meng-Fan Chang; He Qian; Huaqiang Wu (IEEE J. Solid State Circuits, 2021)