Wei Guo

Affiliations:
  • Tianjin University, School of Computer Science and Technology, Tianjin Key Laboratory of Cognitive Computing and Application, China


According to our database1, Wei Guo authored at least 24 papers between 2008 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
A Real-Time Naive Bayes Classifier Accelerator on FPGA.
IEEE Access, 2020

2019
One-round provably secure yoking-proof for RFID applications.
Concurr. Comput. Pract. Exp., 2019

2018
Practical chosen-message CPA attack on message blinding exponentiation algorithm and its efficient countermeasure.
World Wide Web, 2018

2017
A High Efficient Control Flow Authentication Method Basing on Loop Isolation.
Proceedings of the Computer Engineering and Technology - 21st CCF Conference, 2017

Malware Detection with Convolutional Neural Network Using Hardware Events.
Proceedings of the Computer Engineering and Technology - 21st CCF Conference, 2017

2016
SecPage - A Lightweight Memory Protection Architecture.
Proceedings of the 2016 IEEE Trustcom/BigDataSE/ISPA, 2016

Dual Processing Engine Architecture to Speed Up Optimal Ate Pairing on FPGA Platform.
Proceedings of the 2016 IEEE Trustcom/BigDataSE/ISPA, 2016

Micro-architectural Features for Malware Detection.
Proceedings of the Advanced Computer Architecture - 11th Conference, 2016

2015
Fast and Generic Inversion Architectures Over GF(2<sup>m</sup>) Using Modified Itoh-Tsujii Algorithms.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

An Area-Efficient Unified Architecture for Multi-Functional Double-Precision Floating-Point Computation.
J. Circuits Syst. Comput., 2015

A modified post-TnL vertex cache for the multi-shader embedded GPUs.
IEICE Electron. Express, 2015

Combined Attack on Blinded Fault Resistant Exponentiation Algorithm and Efficient Countermeasure.
Proceedings of the 11th International Conference on Computational Intelligence and Security, 2015

2014
A low-time-complexity and secure dual-field scalar multiplication based on co-Z protected NAF.
IEICE Electron. Express, 2014

The Micro-architectural Support Countermeasures against the Branch Prediction Analysis Attack.
Proceedings of the 13th IEEE International Conference on Trust, 2014

Further Research on N-1 Attack against Exponentiation Algorithms.
Proceedings of the Information Security and Privacy - 19th Australasian Conference, 2014

2013
A high performance, area efficient TTA-like vertex shader architecture with optimized floating point arithmetic unit for embedded graphics applications.
Microprocess. Microsystems, 2013

A TTA-like Processor for Fast RSA Key Generation Using RNS.
J. Comput., 2013

A scalable RNS Montgomery multiplier over F<sub>2<sup>m</sup></sub>.
IEICE Electron. Express, 2013

A Unified Cryptographic Processor for RSA and ECC in RNS.
Proceedings of the Computer Engineering and Technology - 17th CCF Conference, 2013

2011
An optimized TTA-like vertex shader datapath for embedded 3D graphics processing unit.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

An Efficient Stereoscopic Game Conversion System for Embedded Platform.
Proceedings of the IEEE 10th International Conference on Trust, 2011

A Novel Architecture for Fast RSA Key Generation Based on RNS.
Proceedings of the Fourth International Symposium on Parallel Architectures, 2011

2009
Design of a Configurable and Extensible Tcore Processor Based on Transport Triggered Architecture.
Proceedings of the CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31, 2009

2008
Design and implementation of co-design toolset for tcore processor.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008


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