Design and implementation of co-design toolset for tcore processor. - Jizeng Wei; Wei Guo 005; Jizhou Sun; Zaifeng Shi (APCCAS, 2008)

Design of a Configurable and Extensible Tcore Processor Based on Transport Triggered Architecture. - Wei Guo 005; Jizeng Wei; Yongbin Yao; Zaifeng Shi; Su Wang (CSIE (3), 2009)

A Novel Architecture for Fast RSA Key Generation Based on RNS. - Jingwei Hu; Wei Guo 005; Jizeng Wei; Yisong Chang; Dazhi Sun (PAAP, 2011)

An Efficient Stereoscopic Game Conversion System for Embedded Platform. - Hao Liu; Wei Guo 005; Chao Lu; Jizeng Wei (TrustCom, 2011)

An optimized TTA-like vertex shader datapath for embedded 3D graphics processing unit. - Jizeng Wei; Yisong Chang; Wei Guo 005; Jizhou Sun (VLSI-SoC, 2011)

A Unified Cryptographic Processor for RSA and ECC in RNS. - Jizeng Wei; Wei Guo 005; Hao Liu; Ya Tan (NCCET, 2013)

A scalable RNS Montgomery multiplier over F2m. - Jingwei Hu; Wei Guo 005; Jizeng Wei; Ray C. C. Cheung (IEICE Electron. Express, 2013)

A TTA-like Processor for Fast RSA Key Generation Using RNS. - Wei Guo 005; Jingwei Hu; Jizeng Wei (J. Comput., 2013)

A high performance, area efficient TTA-like vertex shader architecture with optimized floating point arithmetic unit for embedded graphics applications. - Yisong Chang; Jizeng Wei; Wei Guo 005; Jizhou Sun (Microprocess. Microsystems, 2013)

Further Research on N-1 Attack against Exponentiation Algorithms. - Zhaojing Ding; Wei Guo 005; Liangjian Su; Jizeng Wei; Haihua Gu (ACISP, 2014)

The Micro-architectural Support Countermeasures against the Branch Prediction Analysis Attack. - Ya Tan; Jizeng Wei; Wei Guo 005 (TrustCom, 2014)

A low-time-complexity and secure dual-field scalar multiplication based on co-Z protected NAF. - Jizeng Wei; Xulong Liu; Hao Liu; Wei Guo 005 (IEICE Electron. Express, 2014)

Combined Attack on Blinded Fault Resistant Exponentiation Algorithm and Efficient Countermeasure. - Liangjian Su; Wei Guo 005; Zheng Guo (CIS, 2015)

A modified post-TnL vertex cache for the multi-shader embedded GPUs. - Jizeng Wei; Yisong Chang; Bingchao Li; Wei Guo 005; Jizhou Sun (IEICE Electron. Express, 2015)

An Area-Efficient Unified Architecture for Multi-Functional Double-Precision Floating-Point Computation. - Wei Guo 005; Kwanghyok Ri; Luping Cui; Jizeng Wei (J. Circuits Syst. Comput., 2015)

Fast and Generic Inversion Architectures Over GF(2m) Using Modified Itoh-Tsujii Algorithms. - Jingwei Hu; Wei Guo 005; Jizeng Wei; Ray C. C. Cheung (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Micro-architectural Features for Malware Detection. - Huicheng Peng; Jizeng Wei; Wei Guo 005 (ACA, 2016)

Dual Processing Engine Architecture to Speed Up Optimal Ate Pairing on FPGA Platform. - Zhongyuan Hao; Wei Guo 005; Jizeng Wei; Dazhi Sun (Trustcom/BigDataSE/ISPA, 2016)

SecPage - A Lightweight Memory Protection Architecture. - Kaiyuan Liang; Yanzhao Feng; Jizeng Wei; Wei Guo 005 (Trustcom/BigDataSE/ISPA, 2016)

Malware Detection with Convolutional Neural Network Using Hardware Events. - Wei Guo 005; Tenghai Wang; Jizeng Wei (NCCET, 2017)

A High Efficient Control Flow Authentication Method Basing on Loop Isolation. - Qingran Wang; Wei Guo 005; Dazhi Sun; Jizeng Wei (NCCET, 2017)

Practical chosen-message CPA attack on message blinding exponentiation algorithm and its efficient countermeasure. - Hui Wang; Wei Guo 005; Jizeng Wei (World Wide Web, 2018)

One-round provably secure yoking-proof for RFID applications. - Da-Zhi Sun; Ze-Guang Zhu; Guangquan Xu; Wei Guo 005 (Concurr. Comput. Pract. Exp., 2019)

A Real-Time Naive Bayes Classifier Accelerator on FPGA. - Zhen Xue; Jizeng Wei; Wei Guo 005 (IEEE Access, 2020)