A dynamic-range-improved 2.4GHz WLAN class-E PA combining PWPM and cascode modulation. - Yinsidi Jiao; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (APCCAS, 2012)

A Nonrecursive Digital Calibration Technique for Joint Elimination of Transmitter and Receiver I/Q Imbalances With Minimized Add-On Hardware. - Wei-Han Yu; Chak-Fong Cheang; Pui-In Mak; Weng-Fai Cheng; Ka-Fai Un; U-Wai Lok; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A Combinatorial Impairment-Compensation Digital Predistorter for a Sub-GHz IEEE 802.11af-WLAN CMOS Transmitter Covering a 10x-Wide RF Bandwidth. - Chak-Fong Cheang; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

24.4 A 0.18V 382µW bluetooth low-energy (BLE) receiver with 1.33nW sleep power for energy-harvesting applications in 28nm CMOS. - Wei-Han Yu; Haidong Yi; Pui-In Mak; Jun Yin 001; Rui Paulo Martins (ISSCC, 2017)

A 2.4-GHz ZigBee Transmitter Using a Function-Reuse Class-F DCO-PA and an ADPLL Achieving 22.6% (14.5%) System Efficiency at 6-dBm (0-dBm) Pout. - Xingqiang Peng; Jun Yin 001; Pui-In Mak; Wei-Han Yu; Rui Paulo Martins (IEEE J. Solid State Circuits, 2017)

A High-Voltage-Enabled Class-D Polar PA Using Interactive AM-AM Modulation, Dynamic Matching, and Power-Gating for Average PAE Enhancement. - Wei-Han Yu; Xingqiang Peng; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOS. - Jun Yin 001; Shiheng Yang; Haidong Yi; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (ISSCC, 2018)

A 0.18-V 382-µW Bluetooth Low-Energy Receiver Front-End With 1.33-nW Sleep Power for Energy-Harvesting Applications in 28-nm CMOS. - Haidong Yi; Wei-Han Yu; Pui-In Mak; Jun Yin 001; Rui Paulo Martins (IEEE J. Solid State Circuits, 2018)

A Coin-Battery-Powered LDO-Free 2.4-GHz Bluetooth Low-Energy Transmitter With 34.7% Peak System Efficiency. - Xingqiang Peng; Jun Yin 001; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 0.7-2.5 GHz, 61% EIRP System Efficiency, Four-Element MIMO TX System Exploiting Integrated Power-Relaxed Power Amplifiers and an Analog Spatial De-Interleaver. - Wei-Han Yu; Ka-Fai Un; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 0.2-V Energy-Harvesting BLE Transmitter With a Micropower Manager Achieving 25% System Efficiency at 0-dBm Output and 5.2-nW Sleep Power in 28-nm CMOS. - Shiheng Yang; Jun Yin 001; Haidong Yi; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2019)

A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS. - Chao Fan; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 50.4 GOPs/W FPGA-Based MobileNetV2 Accelerator using the Double-Layer MAC and DSP Efficiency Enhancement. - Jixuan Li; Jiabao Chen; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (A-SSCC, 2021)

A 4-bit Mixed-Signal MAC Array with Swing Enhancement and Local Kernel Memory. - Wei-Han Yu; Massimo Giordano; Rohan Doshi; Minglei Zhang; Pui-In Mak; Rui Paulo Martins; Boris Murmann (MWSCAS, 2021)

An FPGA-Based Energy-Efficient Reconfigurable Convolutional Neural Network Accelerator for Object Recognition Applications. - Jixuan Li; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Design and Implementation of a Low Power Switched-Capacitor-Based Analog Feature Extractor for Voice Keyword Spotting. - Feifei Chen; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (APCCAS, 2022)

A 108nW 0.8mm2 Analog Voice Activity Detector (VAD) Featuring a Time-Domain CNN as a Programmable Feature Extractor and a Sparsity-Aware Computational Scheme in 28nm CMOS. - Feifei Chen; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (ISSCC, 2022)

A 108-nW 0.8-mm2 Analog Voice Activity Detector Featuring a Time-Domain CNN With Sparsity-Aware Computation and Sparsified Quantization in 28-nm CMOS. - Feifei Chen; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

A 47nW Mixed-Signal Voice Activity Detector (VAD) Featuring a Non-Volatile Capacitor-ROM, a Short-Time CNN Feature Extractor and an RNN Classifier. - Jinhai Lin; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (ISSCC, 2023)

A ULP Long-Range Active-RF Tag with Automatic Antenna-Interface Calibration Achieving 20.5% TX Efficiency at -22dBm EIRP, and -60.4dBm Sensitivity at 17.8nW RX Power. - Zhizhan Yang; Jun Yin 001; Wei-Han Yu; Haochen Zhang; Pui-In Mak; Rui Paulo Martins (ISSCC, 2023)

A 1024-Channel 268 nW/pixel 36x36 μm2/ch Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces. - Moon Hyung Jang; Wei-Han Yu; Changuk Lee; Maddy Hays; Pingyu Wang; Nick Vitale; Pulkit Tandon; Pumiao Yan; Pui-In Mak; Youngcheol Chae; E. J. Chichilnisky; Boris Murmann; et al. (VLSI Technology and Circuits, 2023)

An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications. - Zhongyu Zhao; Rujian Cao; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 47-nW Voice Activity Detector (VAD) Featuring a Short-Time CNN Feature Extractor and an RNN-Based Classifier With a Non-Volatile CAP-ROM. - Jinhai Lin; Ka-Fai Un; Wei-Han Yu; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2023)

A 10-bit Two-Stage Pipeline SAR ADC in 55nm CMOS for Compute-in-Memory Applications. - Xiapeng Xu; Yongteng Ma; Xuliang Yu; Fanzi Meng; Wei-Han Yu; Liang Zhao (APCCAS, 2024)

17.9 A 1.8% FAR, 2ms Decision Latency, 1.73nJ/Decision Keywords Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-Domain Computing and Scalable 5T-SRAM. - Fei Tan; Wei-Han Yu; Jinhai Lin; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (ISSCC, 2024)

A 5T-SRAM Based Computing-in-Memory Macro Featuring Partial Sum Boosting and Analog Non-Uniform Quantization. - Guoqiang Xin; Fei Tan; Junde Li; Junren Chen; Wei-Han Yu; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (MWSCAS, 2024)

A 0.05-mm2 2.91-nJ/Decision Keyword-Spotting (KWS) Chip Featuring an Always-Retention 5T-SRAM in 28-nm CMOS. - Fei Tan; Wei-Han Yu; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A 1024-Channel 268-nW/Pixel 36×36 μm2/Channel Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces. - Moon Hyung Jang; Maddy Hays; Wei-Han Yu; Changuk Lee; Pietro Caragiulo; Athanasios T. Ramkaj; Pingyu Wang; A. J. Phillips; Nick Vitale; Pulkit Tandon; Pumiao Yan; Pui-In Mak; et al. (IEEE J. Solid State Circuits, 2024)

A 119.64 GOPs/W FPGA-Based ResNet50 Mixed-Precision Accelerator Using the Dynamic DSP Packing. - Yaozhong Ou; Wei-Han Yu; Ka-Fai Un; Chi-Hang Chan; Yan Zhu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

FLEX-CIM: A Flexible Kernel Size 1-GHz 181.6-TOPS/W 25.63-TOPS/mm2 Analog Compute-in-Memory Macro. - Yuzhao Fu; Wei-Han Yu; Ka-Fai Un; Chi-Hang Chan; Yan Zhu 001; Minglei Zhang; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A ULP Long-Range Active-RF Tag With Automatically Calibrated Antenna-TRX Interface. - Zhizhan Yang; Jun Yin 001; Wei-Han Yu; Haochen Zhang; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A 28-nm 18.7 TOPS/mm² 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh. - Yi Zhan; Wei-Han Yu; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

CLUT-CIM: A Capacitance Lookup Table-Based Analog Compute-in-Memory Macro With Signed-Channel Training and Weight Updating for Nonuniform Quantization. - Yuzhao Fu; Jixuan Li; Wei-Han Yu; Ka-Fai Un; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications. - Rujian Cao; Zhongyu Zhao; Ka-Fai Un; Wei-Han Yu; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 512-nW 0.003-mm² Forward-Forward Closed Box Trainer for an Analog Voice Activity Detector in 28-nm CMOS. - Junde Li; Guoqiang Xin; Wei-Han Yu; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Keyword-Spotting(KWS) Chip Featuring a Bio-Inspired Neuron Model in 65-nm CMOS. - Yantong Liu; Fei Tan; Ka-Fai Un; Wei-Han Yu; Rui Paulo Martins; Pui-In Mak (CNIOT, 2025)

A 94.8nW Battery-Free Intelligent Silicon Platform Enabling Distributed, Adaptive, and Event-Driven Multimodal Sensing at the Edge. - Haochen Zhang; Wei-Han Yu; Zhongyu Zhao; Zhizhan Yang; Ka-Fai Un; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (ISSCC, 2025)

On the Usage of Genetic Algorithms, Reinforcement Learning and Bayesian Optimisation for RF IC Design Automation. - Margarida Lourenço; Bingbing Zhao; Junde Li; Marcelino B. Santos; Pui-In Mak; Rui Paulo Martins; Wei-Han Yu; Fábio Passos (SMACD, 2025)

A 90.7-nW Vibration-Based Condition Monitoring Chip Featuring a Digital Compute-in-Memory- Based DNN Accelerator Using an Ultra-Low-Power 13T-SRAM Cell. - Haochen Zhang; Wei-Han Yu; Zhizhan Yang; Ka-Fai Un; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2025)

A 1.8% FAR, 2 ms Decision Latency, 1.73 nJ/Decision Keywords-Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-IF-Domain Computing and Scalable 5T-SRAM. - Fei Tan; Wei-Han Yu; Jinhai Lin; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2025)

GSLP-CIM: A 28-nm Globally Systolic and Locally Parallel CNN/Transformer Accelerator With Scalable and Reconfigurable eDRAM Compute-in-Memory Macro for Flexible Dataflow. - Yi Zhan; Wei-Han Yu; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A 28-nm MFCC-Free Keyword Switchable Keyword Spotting (KWS) System With Transferred Training Algorithm. - Fei Tan; Yujia Wang; Wei-Han Yu; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

An 800-MHz 8.17-TOPS/W 0.63-TOPS/mm2 Memory-Utilization-Aware CNN Accelerator Featuring a Memory Stationary Dataflow. - Jixuan Li; Ke Li; Ka-Fai Un; Wei-Han Yu; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2025)

A 97.8 GOPS/W FPGA-Based Residual-Block-Aware CNN Accelerator Featuring Multi-Clock PW2 Pipeline and Adaptive-Resolution Quantization. - Jixuan Li; Ke Li; Ka-Fai Un; Wei-Han Yu; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)