A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates. - How-Rern Lin; Wei-Hao Chiu; Tsung-Yi Wu (IEICE Trans. Electron., 2009)

A 5-GHz fractional-N phase-locked loop with spur reduction technique in 0.13-μm CMOS. - Wei-Hao Chiu; Chien-Yuan Cheng; Tsung-Hsien Lin (ISCAS, 2010)

A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops. - Wei-Hao Chiu; Yu-Hsiang Huang; Tsung-Hsien Lin (IEEE J. Solid State Circuits, 2010)

A 4MHz BW 69dB SNDR continuous-time delta-sigma modulator with reduced sensitivity to clock jitter. - Yu-Cheng Chang; Wei-Hao Chiu; Chen-Chien Lin; Tsung-Hsien Lin (A-SSCC, 2011)

A Synchronous 50% Duty-Cycle Clock Generator in 0.35- μ m CMOS. - Tsung-Hsien Lin; Chao-Ching Chi; Wei-Hao Chiu; Yu-Hsiang Huang (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Low-complexity architecture of carrier frequency offset estimation and compensation for body area network systems. - Kuang-Hao Lin; Wei-Hao Chiu; Jan-Dong Tseng (Comput. Math. Appl., 2012)

10.3 A 12nm CMOS RF Transceiver Supporting 4G/5G UL MIMO. - Ming-Da Tsai; Song-Yu Yang; Chi-Yao Yu; Ping-Yu Chen; Tzung-Han Wu; Mohammed Hassan; Chi-Tsan Chen; Chao-Wei Wang; Yen-Chuan Huang; Li-Han Hung; Wei-Hao Chiu; Anson Lin; et al. (ISSCC, 2020)

RFIC and RF Module for 5G Applications. - Ming-Da Tsai; Song-Yu Yang; Chi-Yao Yu; Ping-Yu Chen; Tzung-Han Wu; Mohammed Hassan; Chi-Tsan Chen; Chao-Wei Wang; Yen-Chuan Huang; Li-Han Huang; Wei-Hao Chiu; Anson Lin; et al. (VLSI-DAT, 2020)