We stand with Ukraine  

Wei He

Orcid: 0000-0002-2628-8028

Affiliations:
  • China Telecom BestPay Coompany Ltd., Shanghai, China
  • Technical University of Madrid, Spain (PhD 2014)


According to our database1, Wei He authored at least 9 papers between 2011 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2022
PipeFL: Hardware/Software co-Design of an FPGA Accelerator for Federated Learning.
[BibTeX]
[DOI]
Zixiao Wang
,
Biyao Che
,
Liang Guo
,
Yang Du
,
Ying Chen
,
Jizhuang Zhao
,
Wei He
IEEE Access, 2022

2021
Pushing the Limit of PFA: Enhanced Persistent Fault Analysis on Block Ciphers.
[BibTeX]
[DOI]
Guorui Xu
,
Fan Zhang
,
Bolin Yang
,
Xinjie Zhao
,
Wei He
,
Kui Ren
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

2020
Side-Channel Analysis and Countermeasure Design on ARM-Based Quantum-Resistant SIKE.
[BibTeX]
[DOI]
Fan Zhang
,
Bolin Yang
,
Xiaofei Dong
,
Sylvain Guilley
,
Zhe Liu
,
Wei He
,
Fangguo Zhang
,
Kui Ren
IEEE Trans. Computers, 2020

2018
Persistent Fault Analysis on Block Ciphers.
[BibTeX]
[DOI]
Fan Zhang
,
Xiaoxuan Lou
,
Xinjie Zhao
,
Shivam Bhasin
,
Wei He
,
Ruyi Ding
,
Samiya Qureshi
,
Kui Ren
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

2015
Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis.
[BibTeX]
[DOI]
Wei He
,
Shivam Bhasin
,
Andrés Otero
,
Tarik Graba
,
Eduardo de la Torre
,
Jean-Luc Danger
IET Inf. Secur., 2015

2014
Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic.
[BibTeX]
[DOI]
Wei He
,
Andrés Otero
,
Eduardo de la Torre
,
Teresa Riesgo
Microprocess. Microsystems, 2014

2012
Automatic generation of identical routing pairs for FPGA implemented DPL logic.
[BibTeX]
[DOI]
Wei He
,
Andrés Otero
,
Eduardo de la Torre
,
Teresa Riesgo
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation.
[BibTeX]
[DOI]
Wei He
,
Eduardo de la Torre
,
Teresa Riesgo
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2012

2011
A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations.
[BibTeX]
[DOI]
Wei He
,
Eduardo de la Torre
,
Teresa Riesgo
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011


  Loading...