A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations. - Wei He 015; Eduardo de la Torre; Teresa Riesgo (ReConFig, 2011)

An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation. - Wei He 015; Eduardo de la Torre; Teresa Riesgo (COSADE, 2012)

Automatic generation of identical routing pairs for FPGA implemented DPL logic. - Wei He 015; Andrés Otero; Eduardo de la Torre; Teresa Riesgo (ReConFig, 2012)

Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic. - Wei He 015; Andrés Otero; Eduardo de la Torre; Teresa Riesgo (Microprocess. Microsystems, 2014)

Dual-rail active protection system against side-channel analysis in FPGAs. - Wei He 015; Dirmanto Jap (ASAP, 2015)

Multiple Fault Attack on PRESENT with a Hardware Trojan Implementation in FPGA. - Jakub Breier; Wei He 015 (SIoT, 2015)

Process Variation Evaluation Using RO PUF for Enhancing SCA-Resistant Dual-Rail Implementation. - Wei He 015; Dirmanto Jap; Alexander Herrmann (WISA, 2015)

Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis. - Wei He 015; Shivam Bhasin; Andrés Otero; Tarik Graba; Eduardo de la Torre; Jean-Luc Danger (IET Inf. Secur., 2015)

Exploiting FPGA Block Memories for Protected Cryptographic Implementations. - Shivam Bhasin; Jean-Luc Danger; Sylvain Guilley; Wei He 015 (ACM Trans. Reconfigurable Technol. Syst., 2015)

Supervised and unsupervised machine learning for side-channel based Trojan detection. - Dirmanto Jap; Wei He 015; Shivam Bhasin (ASAP, 2016)

Bypassing Parity Protected Cryptography using Laser Fault Injection in Cyber-Physical System. - Wei He 015; Jakub Breier; Shivam Bhasin; Anupam Chattopadhyay (CPSS@AsiaCCS, 2016)

PLL to the rescue: a novel EM fault countermeasure. - Noriyuki Miura; Zakaria Najm; Wei He 015; Shivam Bhasin; Xuan Thuy Ngo; Makoto Nagata; Jean-Luc Danger (DAC, 2016)

Ring Oscillator under Laser: Potential of PLL-based Countermeasure against Laser Fault Injection. - Wei He 015; Jakub Breier; Shivam Bhasin; Noriyuki Miura; Makoto Nagata (FDTC, 2016)

Cheap and Cheerful: A Low-Cost Digital Sensor for Detecting Laser Fault Injection Attacks. - Wei He 015; Jakub Breier; Shivam Bhasin (SPACE, 2016)

Comprehensive Laser Sensitivity Profiling and Data Register Bit-Flips for Cryptographic Fault Attacks in 65 Nm FPGA. - Wei He 015; Jakub Breier; Shivam Bhasin; Dirmanto Jap; Hock Guan Ong; Chee Lip Gan (SPACE, 2016)

An FPGA-compatible PLL-based sensor against fault injection attack. - Wei He 015; Jakub Breier; Shivam Bhasin; Noriyuki Miura; Makoto Nagata (ASP-DAC, 2017)

An electromagnetic fault injection sensor using Hogge phase-detector. - Jakub Breier; Shivam Bhasin; Wei He 015 (ISQED, 2017)

Transistor level SCA-resistant scheme based on fluctuating power logic. - Liang Geng; Fan Zhang 010; Jizhong Shen; Wei He 015; Shivam Bhasin; Xinjie Zhao 001; Shize Guo (Sci. China Inf. Sci., 2017)

Low-cost design of stealthy hardware trojan for bit-level fault attacks on block ciphers. - Fan Zhang 010; Xinjie Zhao 001; Wei He 015; Shivam Bhasin; Shize Guo (Sci. China Inf. Sci., 2017)

Extensive Laser Fault Injection Profiling of 65 nm FPGA. - Jakub Breier; Wei He 015; Shivam Bhasin; Dirmanto Jap; Samuel Chef; Hock Guan Ong; Chee Lip Gan (J. Hardw. Syst. Secur., 2017)

Attacks in Reality: the Limits of Concurrent Error Detection Codes Against Laser Fault Injection. - Jakub Breier; Wei He 015; Dirmanto Jap; Shivam Bhasin; Anupam Chattopadhyay (J. Hardw. Syst. Secur., 2017)

Stealthy Hardware Trojan Based Algebraic Fault Analysis of HIGHT Block Cipher. - Hao Chen 003; Tao Wang 008; Fan Zhang 010; Xinjie Zhao 001; Wei He 015; Lumin Xu; Yunfei Ma (Secur. Commun. Networks, 2017)

The Conflicted Usage of RLUTs for Security-Critical Applications on FPGA. - Debapriya Basu Roy; Shivam Bhasin; Jean-Luc Danger; Sylvain Guilley; Wei He 015; Debdeep Mukhopadhyay; Zakaria Najm; Xuan Thuy Ngo (J. Hardw. Syst. Secur., 2018)

Persistent Fault Analysis on Block Ciphers. - Fan Zhang 010; Xiaoxuan Lou; Xinjie Zhao 001; Shivam Bhasin; Wei He 015; Ruyi Ding; Samiya Qureshi; Kui Ren 001 (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018)

Side-Channel Analysis and Countermeasure Design on ARM-Based Quantum-Resistant SIKE. - Fan Zhang 010; Bolin Yang; Xiaofei Dong; Sylvain Guilley; Zhe Liu 001; Wei He 015; Fangguo Zhang; Kui Ren 001 (IEEE Trans. Computers, 2020)

Decentralized and expressive data publish-subscribe scheme in cloud based on attribute-based keyword search. - Qian Xu 008; Qing Zhang; Bo Yu; Nandi Shi; Changshuai Wang; Wei He 015 (J. Syst. Archit., 2021)

Pushing the Limit of PFA: Enhanced Persistent Fault Analysis on Block Ciphers. - Guorui Xu; Fan Zhang 010; Bolin Yang; Xinjie Zhao 001; Wei He 015; Kui Ren 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

PipeFL: Hardware/Software co-Design of an FPGA Accelerator for Federated Learning. - Zixiao Wang 003; Biyao Che; Liang Guo 003; Yang Du; Ying Chen; Jizhuang Zhao; Wei He 015 (IEEE Access, 2022)

HQsFL: A Novel Training Strategy for Constructing High-performance and Quantum-safe Federated Learning. - Bo Yu; Huajie Shen; Qian Xu 008; Wei He 015; Wankui Mao; Qing Zhang; Fan Zhang 010 (AsiaCCS, 2024)

A Scalable Private Data Alignment Scheme for Arbitrary Participants Using Oblivious PRF. - Yuhan Yang; Qian Xu 008; Wei He 015; Nandi Shi; Huajie Shen; Bo Yu; Lijun Wei; Jing Wu 006; Chengnian Long (IEEE Internet Things J., 2025)