A Low-Voltage PLL Design Using a New Calibration Technique for Low-Power Implantable Biomedical Systems. - Yu-Lung Lo; Wei-Hsiang Ho (Circuits Syst. Signal Process., 2017)

A 25-Gb/s, 2.1-pJ/bit, Fully Integrated Optical Receiver With a Baud-Rate Clock and Data Recovery. - Yuan-Sheng Lee; Wei-Hsiang Ho; Wei-Zen Chen (IEEE J. Solid State Circuits, 2019)

A 32 Gb/s PAM-4 Optical Transceiver With Active Back Termination in 40 nm CMOS Technology. - Wei-Hsiang Ho; Yi-Hsun Hsieh; Boris Murmann; Wei-Zen Chen (IEEE Open J. Circuits Syst., 2021)