High-speed sensing scheme for CMOS DRAMs. - Sang H. Dhong; Nicky Chau-Chun Lu; Wei Hwang; Stephen A. Parke (IEEE J. Solid State Circuits, 1988)

Large-signal 2T, 1C DRAM cell: signal and layout analysis. - Walter H. Henkels; Wei Hwang (IEEE J. Solid State Circuits, 1994)

A Pulse-To-Static Conversion Latch with a Self-Timed Control Circuit. - Wei Hwang; Rajiv V. Joshi; Walter H. Henkels (ICCD, 1997)

Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. - W. K. Luk; Yasunao Katayama; Wei Hwang; Matthew R. Wordeman; Toshiaki Kirihata; Akashi Satoh; Seiji Munetoh; Hing Wong; B. El-Kareh; P. Xiao; Rajiv V. Joshi (ICCD, 1997)

Design and implementation of differential cascode voltage switch with pass-gate (DCVSPG) logic for high-performance digital systems. - Fang-Shi Lai; Wei Hwang (IEEE J. Solid State Circuits, 1997)

Design and implementation of high performance dynamic 64-bit parallel adder with enhanced testability. - Wei Hwang; George Diedrich Gristede; Pia N. Sanda; Shao Y. Wang; David F. Heidel (CICC, 1998)

Design Considerations and Implementation of a High Performance Dynamic Register File. - Rajiv V. Joshi; Wei Hwang (VLSI Design, 1999)

Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability. - Wei Hwang; George Diedrich Gristede; Pia N. Sanda; Shao Y. Wang; David F. Heidel (IEEE J. Solid State Circuits, 1999)

A 500-MHz, 32-word×64-bit, eight-port self-resetting CMOS register file. - Wei Hwang; Rajiv V. Joshi; Walter H. Henkels (IEEE J. Solid State Circuits, 1999)

A comparison of dual-rail pass transistor logic families in 1.5V, 0.18µm CMOS technology for low power applications. - George Gristede; Wei Hwang (ACM Great Lakes Symposium on VLSI, 2000)

"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session). - Rajiv V. Joshi; Wei Hwang; S. C. Wilson; Ching-Te Chuang (ISLPED, 2000)

A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology. - Rajiv V. Joshi; Wei Hwang; S. C. Wilson; Ghavam V. Shahidi; Ching-Te Chuang (VLSI Design, 2000)

A scannable pulse-to-static conversion register array for self-timed circuits. - Wei Hwang; Rajiv V. Joshi; George Gristede (IEEE J. Solid State Circuits, 2000)

SOI for asynchronous dynamic circuits. - Rajiv V. Joshi; Wei Hwang; Ching-Te Chuang (ACM Great Lakes Symposium on VLSI, 2001)

Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design. - W. Chen; Wei Hwang; Prabhakar Kudva; George Gristede; Stephen V. Kosonocky; Rajiv V. Joshi (ISLPED, 2001)

Design Of Provably Correct Storage Arrays. - Rajiv V. Joshi; Wei Hwang; Andreas Kuehlmann (VLSI Design, 2001)

Multiplier architecture power consumption characterization for low-power DSP applications. - Sangjin Hong; Shu-Shin Chin; Suhwan Kim 001; Wei Hwang (ICECS, 2002)

Low-power circuits and technology for wireless digital systems. - Stephen V. Kosonocky; Azeez J. Bhavnagarwala; Kenneth Chin; George Gristede; Anne-Marie Haen; Wei Hwang; Mark B. Ketchen; Suhwan Kim 001; Daniel R. Knebel; Kevin W. Warren; Victor V. Zyuban (IBM J. Res. Dev., 2003)

Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization. - Sangjin Hong; Shu-Shin Chin; Suhwan Kim 001; Wei Hwang (J. VLSI Signal Process., 2004)

Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits. - Chung-Hsien Hua; Wei Hwang; Chih-Kai Chen (ISCAS (1), 2005)

Distributed data-retention power gating techniques for column and row co-controlled embedded SRAM. - Chung-Hsien Hua; Tung-Shuan Cheng; Wei Hwang (MTDT, 2005)

Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory. - Po-Tsang Huang; Wei-Keng Chang; Wei Hwang (APCCAS, 2006)

A Low-Power Reconfigurable Mixed-Radix FFT/IFFT Processor. - Chi-Chen Lai; Wei Hwang (APCCAS, 2006)

On-Chip DC-DC Converter with Frequency Detector for Dynamic Voltage Scaling Technology. - Jen-Wei Yang; Po-Tsang Huang; Wei Hwang (APCCAS, 2006)

A 1.7mW all digital phase-locked loop with new gain generator and low power DCO. - Tzu-Chiang Chao; Wei Hwang (ISCAS, 2006)

A noise-tolerant matchline scheme with XOR-based conditional keeper for energy-efficient TCAM. - Chung-Hsien Hua; Chi-Wei Peng; Wei Hwang (ISCAS, 2006)

2-level FIFO architecture design for switch fabrics in network-on-chip. - Po-Tsang Huang; Wei Hwang (ISCAS, 2006)

A 1.9mW Portable ADPLL-based Frequency Synthesizer for High Speed Clock Generation. - Ming-Hung Chang; Zong-Xi Yang; Wei Hwang (ISCAS, 2007)

Low Power On-Chip Current Monitoring Medium-Grained Adaptive Voltage Control. - Wei-Chih Hsieh; Wei Hwang (ISCAS, 2007)

A flexible two-layer external memory management for H.264/AVC decoder. - Chang-Hsuan Chang; Ming-Hung Chang; Wei Hwang (SoCC, 2007)

A 65nm low power 2T1D embedded DRAM with leakage current reduction. - Mu-Tien Chang; Po-Tsang Huang; Wei Hwang (SoCC, 2007)

A fully-differential subthreshold SRAM cell with auto-compensation. - Mu-Tien Chang; Wei Hwang (APCCAS, 2008)

A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop. - Li-Pu Chuang; Ming-Hung Chang; Po-Tsang Huang; Chih-Hao Kan; Wei Hwang (ISCAS, 2008)

"Green" micro-architecture and circuit co-design for ternary content addressable memory. - Po-Tsang Huang; Shu-Wei Chang; Wen-Yen Liu; Wei Hwang (ISCAS, 2008)

Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip. - Po-Tsang Huang; Wei-Li Fang; Yin-Ling Wang; Wei Hwang (NOCS, 2008)

A 300-mV 36-muW multiphase dual digital clock output generator with self-calibration. - Ming-Hung Chang; Li-Pu Chuang; I-Ming Chang; Wei Hwang (SoCC, 2008)

A robust ultra-low power asynchronous FIFO memory with self-adaptive power control. - Mu-Tien Chang; Po-Tsang Huang; Wei Hwang (SoCC, 2008)

In-situ self-aware adaptive power control system with multi-mode power gating network. - Wei-Chih Hsieh; Wei Hwang (SoCC, 2008)

Low-power floating bitline 8-T SRAM design with write assistant circuits. - Hao-I Yang; Ssu-Yun Lai; Wei Hwang (SoCC, 2008)

Impacts of NBTI and PBTI on Power-gated SRAM with High-k Metal-gate Devices. - Hao-I Yang; Ching-Te Chuang; Wei Hwang (ISCAS, 2009)

A 2.1-mW 0.3V-1.0V wide locking range multiphase DLL using self-estimated SAR algorithm. - Yi-Ming Chang; Ming-Hung Chang; Wei Hwang (SoCC, 2009)

An adaptive congestion-aware routing algorithm for mesh network-on-chip platform. - Po-Tsang Huang; Wei Hwang (SoCC, 2009)

High efficiency power management system for solar energy harvesting applications. - Ming-Hung Chang; Jung-Yi Wu; Wei-Chih Hsieh; Shang-Yuan Lin; You-Wei Liang; Wei Hwang (APCCAS, 2010)

Fully on-chip temperature, process, and voltage sensors. - Shi-Wen Chen; Ming-Hung Chang; Wei-Chih Hsieh; Wei Hwang (ISCAS, 2010)

Low quiescent current variable output digital controlled voltage regulator. - Wei-Chih Hsieh; Wei Hwang (ISCAS, 2010)

Power noise suppression technique using active decoupling capacitor for TSV 3D integration. - Tien-Hung Lin; Po-Tsang Huang; Wei Hwang (SoCC, 2010)

A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder. - Po-Tsang Huang; Xin-Ru Lee; Hsie-Chia Chang; Chen-Yi Lee; Wei Hwang (J. Low Power Electron., 2010)

A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS. - Ming-Hung Chang; Yi-Te Chiu; Shu-Lin Lai; Wei Hwang (ISLPED, 2011)

Near-/sub-threshold DLL-based clock generator with PVT-aware locking range compensation. - Ming-Hung Chang; Chung-Ying Hsieh; Mei-Wei Chen; Wei Hwang (ISLPED, 2011)

An energy-efficient 10T SRAM-based FIFO memory operating in near-/sub-threshold regions. - Wei-Hung Du; Ming-Hung Chang; Hao-Yi Yang; Wei Hwang (SoCC, 2011)

On-demand memory sub-system for multi-core SoCs. - Po-Tsang Huang; Yung Chang; Wei Hwang (SoCC, 2011)

A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. - Hao-I Yang; Shih-Chi Yang; Mao-Chih Hsia; Yung-Wei Lin; Yi-Wei Lin; Chien-Hen Chen; Chi-Shin Chang; Geng-Cing Lin; Yin-Nien Chen; Ching-Te Chuang; Wei Hwang; Shyh-Jye Jou; et al. (SoCC, 2011)

Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks. - Po-Tsang Huang; Wei Hwang (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

A 65 nm 0.165 fJ/Bit/Search 256 , ˟, 144 TCAM Macro Design for IPv6 Lookup Tables. - Po-Tsang Huang; Wei Hwang (IEEE J. Solid State Circuits, 2011)

Impacts of gate-oxide breakdown on power-gated SRAM. - Hao-I Yang; Wei Hwang; Ching-Te Chuang (Microelectron. J., 2011)

Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM. - Hao-I Yang; Shyh-Chyi Yang; Wei Hwang; Ching-Te Chuang (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Adaptive Power Control Technique on Power-Gated Circuitries. - Wei-Chih Hsieh; Wei Hwang (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-kappa Metal-Gate Devices. - Hao-I Yang; Wei Hwang; Ching-Te Chuang (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Substrate noise suppression technique for power integrity of TSV 3D integration. - Po-Jen Yang; Po-Tsang Huang; Wei Hwang (ISCAS, 2012)

High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder. - Hao-I Yang; Yi-Wei Lin; Mao-Chih Hsia; Geng-Cing Lin; Chi-Shin Chang; Yin-Nien Chen; Ching-Te Chuang; Wei Hwang; Shyh-Jye Jou; Nan-Chun Lien; Hung-Yu Li; Kuen-Di Lee; et al. (ISCAS, 2012)

A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist. - Yi-Wei Lin; Hao-I Yang; Geng-Cing Lin; Chi-Shin Chang; Ching-Te Chuang; Wei Hwang; Chia-Cheng Chen; Willis Shih; Huan-Shun Huang (ISLPED, 2012)

An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operation. - Mei-Wei Chen; Ming-Hung Chang; Yuan-Hua Chu; Wei Hwang (SoCC, 2012)

On-chip self-calibrated process-temperature sensor for TSV 3D integration. - Tzu-Ting Chiang; Po-Tsang Huang; Ching-Te Chuang; Kuan-Neng Chen; Jin-Chern Chiou; Kuo-Hua Chen; Chi-Tsung Chiu; Ho-Ming Tong; Wei Hwang (SoCC, 2012)

A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist. - Yung-Wei Lin; Hao-I Yang; Mao-Chih Hsia; Yi-Wei Lin; Chien-Hen Chen; Ching-Te Chuang; Wei Hwang; Nan-Chun Lien; Kuen-Di Lee; Wei-Chiang Shih; Ya-Ping Wu; Wen-Ta Lee; et al. (SoCC, 2012)

A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs. - Wei-Hung Du; Po-Tsang Huang; Ming-Hung Chang; Wei Hwang (VLSI-DAT, 2012)

An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array. - Yi-Wei Lin; Ming-Chien Tsai; Hao-I Yang; Geng-Cing Lin; Shao-Cheng Wang; Ching-Te Chuang; Shyh-Jye Jou; Wei Hwang; Nan-Chun Lien; Kuen-Di Lee; Wei-Chiang Shih (VLSI-DAT, 2012)

Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array. - Ming-Chien Tsai; Yi-Wei Lin; Hao-I Yang; Ming-Hsien Tu; Wei-Chiang Shih; Nan-Chun Lien; Kuen-Di Lee; Shyh-Jye Jou; Ching-Te Chuang; Wei Hwang (VLSI-DAT, 2012)

Self-Calibrated Energy-Efficient and Reliable Channels for On-Chip Interconnection Networks. - Po-Tsang Huang; Wei Hwang (J. Electr. Comput. Eng., 2012)

A 0.4 V 520 nW 990 μm2 Fully Integrated Frequency-Domain Smart Temperature Sensor in 65 nm CMOS. - Ming-Hung Chang; Shang-Yuan Lin; Wei Hwang (J. Low Power Electron., 2012)

A 45 nm 10T Dual-Port SRAM with Shared Bit-Line Scheme for Low Power Operation. - Dao-Ping Wang; Wei Hwang (J. Low Power Electron., 2012)

Design and Iso-Area Vmin Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS. - Ming-Hung Chang; Yi-Te Chiu; Wei Hwang (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A 0.33-V, 500-kHz, 3.94-µW 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist. - Chien-Yu Lu; Ming-Hsien Tu; Hao-I Yang; Ya-Ping Wu; Huan-Shun Huang; Yuh-Jiun Lin; Kuen-Di Lee; Yung-Shin Kao; Ching-Te Chuang; Shyh-Jye Jou; Wei Hwang (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

All Digital Linear Voltage Regulator for Super- to Near-Threshold Operation. - Wei-Chih Hsieh; Wei Hwang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Low temperature (<180 °C) bonding for 3D integration. - Yan-Pin Huang; Ruoh-Ning Tzeng; Yu-San Chien; Ming-Shaw Shy; Teu-Hua Lin; Kuo-Hua Chen; Ching-Te Chuang; Wei Hwang; Chi-Tsung Chiu; Ho-Ming Tong; Kuan-Neng Chen (3DIC, 2013)

Area-power-efficient 11-bit SAR ADC with delay-line enhanced tuning for neural sensing applications. - Teng-Chieh Huang; Po-Tsang Huang; Shang-Lin Wu; Kuan-Neng Chen; Jin-Chern Chiou; Kuo-Hua Chen; Chi-Tsung Chiu; Ho-Ming Tong; Ching-Te Chuang; Wei Hwang (BioCAS, 2013)

Near-/Sub-Vth process, voltage, and temperature (PVT) sensors with dynamic voltage selection. - Ming-Hung Chang; Shang-Yuan Lin; Pei-Chen Wu; Olesya Zakoretska; Ching-Te Chuang; Kuan-Neng Chen; Chen-Chao Wang; Kuo-Hua Chen; Chi-Tsung Chiu; Ho-Ming Tong; Wei Hwang (ISCAS, 2013)

A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. - Chi-Shin Chang; Hao-I Yang; Wei-Nan Liao; Yi-Wei Lin; Nan-Chun Lien; Chien-Hen Chen; Ching-Te Chuang; Wei Hwang; Shyh-Jye Jou; Ming-Hsien Tu; Huan-Shun Huang; Yong-Jyun Hu; et al. (ISCAS, 2013)

Through-silicon-via-based double-side integrated microsystem for neural sensing applications. - Chih-Wei Chang; Po-Tsang Huang; Lei-Chun Chou; Shang-Lin Wu; Shih-Wei Lee; Ching-Te Chuang; Kuan-Neng Chen; Jin-Chern Chiou; Wei Hwang; Yen-Chi Lee; Chung-Hsi Wu; Kuo-Hua Chen; et al. (ISSCC, 2013)

A dual-edged triggered explicit-pulsed level converting flip-flop with a wide operation range. - Mei-Wei Chen; Ming-Hung Chang; Pei-Chen Wu; Yi-Ping Kuo; Chun-Lin Yang; Yuan-Hua Chu; Wei Hwang (SoCC, 2013)

A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control. - Wei-Nan Liao; Nan-Chun Lien; Chi-Shin Chang; Li-Wei Chu; Hao-I Yang; Ching-Te Chuang; Shyh-Jye Jou; Wei Hwang; Ming-Hsien Tu; Huan-Shun Huang; Jian-Hao Wang; Paul-Sen Kan; et al. (SoCC, 2013)

A Two-Write and Two-Read Multi-Port SRAM with Shared Write Bit-Line Scheme and Selective Read Path for Low Power Operation. - Dao-Ping Wang; Hon-Jarn Lin; Wei Hwang (J. Low Power Electron., 2013)

0.339fJ/bit/search energy-efficient TCAM macro design in 40nm LP CMOS. - Po-Tsang Huang; Shu-Lin Lai; Ching-Te Chuang; Wei Hwang; Jason Huang; Angelo Hu; Paul Kan; Michael Jia; Kimi Lv; Bright Zhang (A-SSCC, 2014)

A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC. - Sang H. Dhong; Richard Guo; Ming-Zhang Kuo; Ping-Lin Yang; Cheng-Chung Lin; Kevin Huang 005; Min-Jer Wang; Wei Hwang (CICC, 2014)

A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS. - Ming-Zhang Kuo; Henry Hsieh; Sang H. Dhong; Ping-Lin Yang; Cheng-Chung Lin; Ryan Tseng; Kevin Huang 005; Min-Jer Wang; Wei Hwang (CICC, 2014)

Energy-efficient configurable discrete wavelet transform for neural sensing applications. - Tang-Hsuan Wang; Po-Tsang Huang; Kuan-Neng Chen; Jin-Chern Chiou; Kuo-Hua Chen; Chi-Tsung Chiu; Ho-Ming Tong; Ching-Te Chuang; Wei Hwang (ISCAS, 2014)

18.6 2.5D heterogeneously integrated bio-sensing microsystem for multi-channel neural-sensing applications. - Po-Tsang Huang; Lei-Chun Chou; Teng-Chieh Huang; Shang-Lin Wu; Tang-Shuan Wang; Yu-Rou Lin; Chuan-An Cheng; Wen-Wei Shen; Kuan-Neng Chen; Jin-Chern Chiou; Ching-Te Chuang; Wei Hwang; et al. (ISSCC, 2014)

Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video. - Chih-Yuan Chang; Po-Tsang Huang; Yi-Chun Chen; Tian-Sheuan Chang; Wei Hwang (SoCC, 2014)

PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems. - Pei-Chen Wu; Yi-Ping Kuo; Chung-Shiang Wu; Ching-Te Chuang; Yuan-Hua Chu; Wei Hwang (SoCC, 2014)

Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition. - Shang-Lin Wu; Po-Tsang Huang; Teng-Chieh Huang; Kuan-Neng Chen; Jin-Chern Chiou; Kuo-Hua Chen; Chi-Tsung Chiu; Ho-Ming Tong; Ching-Te Chuang; Wei Hwang (VLSI-DAT, 2014)

2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications. - Po-Tsang Huang; Shang-Lin Wu; Yu-Chieh Huang; Lei-Chun Chou; Teng-Chieh Huang; Tang-Hsuan Wang; Yu-Rou Lin; Chuan-An Cheng; Wen-Wei Shen; Ching-Te Chuang; Kuan-Neng Chen; Jin-Chern Chiou; et al. (IEEE Trans. Biomed. Circuits Syst., 2014)

A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist. - Nan-Chun Lien; Li-Wei Chu; Chien-Hen Chen; Hao-I Yang; Ming-Hsien Tu; Paul-Sen Kan; Yong-Jyun Hu; Ching-Te Chuang; Shyh-Jye Jou; Wei Hwang (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors. - Dao-Ping Wang; Hon-Jarn Lin; Ching-Te Chuang; Wei Hwang (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology. - Henry Hsieh; Sang H. Dhong; Cheng-Chung Lin; Ming-Zhang Kuo; Kuo-Feng Tseng; Ping-Lin Yang; Kevin Huang 005; Min-Jer Wang; Wei Hwang (CICC, 2015)

An all-digital power management unit with 90% power efficiency and ns-order voltage transition time for DVS operation in low power sensing SoC applications. - Chung-Shiang Wu; Kai-Chun Lin; Yi-Ping Kuo; Po-Hung Chen; Yuan-Hua Chu; Wei Hwang (ISCAS, 2015)

Energy-efficient gas recognition system with event-driven power control. - Chun-Ying Huang; Po-Tsang Huang; Chih-Chao Yang; Ching-Te Chuang; Wei Hwang (SoCC, 2015)

All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction. - Yi-Ping Kuo; Po-Tsang Huang; Chung-Shiang Wu; Yu-Jie Liang; Ching-Te Chuang; Yuan-Hua Chu; Wei Hwang (VLSI-DAT, 2015)

Low power algorithm-architecture co-design of fast Independent Component Analysis (FICA) for multi-gas sensor applications. - Chih-Chao Yang; Po-Tsang Huang; Chun-Ying Huang; Ching-Te Chuang; Wei Hwang (VLSI-DAT, 2015)

An ultra-high-density 256-channel/25mm2 neural sensing microsystem using TSV-embedded neural probes. - Yu-Chieh Huang; Po-Tsang Huang; Shang-Lin Wu; Yu-Chen Hu; Yan-Huei You; Ming Chen; Yan-Yu Huang; Hsiao-Chun Chang; Yen-Han Lin; Jeng-Ren Duann; Tzai-Wen Chiu; Wei Hwang; et al. (ISCAS, 2016)

Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application. - Ming Chen; Po-Tsang Huang; Shang-Lin Wu; Wei Hwang; Ching-Te Chuang (SoCC, 2016)

An implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable μ-needle array and flexible interposer. - Po-Tsang Huang; Yu-Chieh Huang; Shang-Lin Wu; Yu-Chen Hu; Ming-Wei Lu; Ting-Wei Sheng; Fung-Kai Chang; Chun-Pin Lin; Nien-Shang Chang; Hung-Lieh Chen; Chi-Shi Chen; Jeng-Ren Duann; et al. (ISCAS, 2017)

Wide-I/O 3D-staked DRAM controller for near-data processing system. - Yu-Hsuan Lin; Shih-Fan Peng; Wei Hwang (VLSI-DAT, 2017)

Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes. - Yu-Chieh Huang; Po-Tsang Huang; Shang-Lin Wu; Yu-Chen Hu; Yan-Huei You; Ming Chen; Yan-Yu Huang; Hsiao-Chun Chang; Yen-Han Lin; Jeng-Ren Duann; Tzai-Wen Chiu; Wei Hwang; et al. (IEEE Trans. Biomed. Circuits Syst., 2017)

A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist. - Shang-Lin Wu; Kuang-Yu Li; Po-Tsang Huang; Wei Hwang; Ming-Hsien Tu; Sheng-Chi Lung; Wei-Sheng Peng; Huan-Shun Huang; Kuen-Di Lee; Yung-Shin Kao; Ching-Te Chuang (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Digital Buck Converter With Switching Loss Reduction Scheme for Light Load Efficiency Enhancement. - Chung-Shiang Wu; Hui-Hsuan Lee; Po-Hung Chen; Wei Hwang (IEEE Trans. Very Large Scale Integr. Syst., 2017)

0.4V Reconfigurable Near-Threshold TCAM in 28nm High-k Metal-Gate CMOS Process. - Yun-Sheng Chan; Po-Tsang Huang; Shang-Lin Wu; Sheng-Chi Lung; Wei-Chang Wang; Wei Hwang; Ching-Te Chuang (SoCC, 2018)

28nm near/sub-threshold dual-port FIFO memory for shared queues in multi-sensor applications. - Yi-Chun Wu; Po-Tsang Huang; Shang-Lin Wu; Sheng-Chi Lung; Wei-Chang Wang; Wei Hwang; Ching-Te Chuang (VLSI-DAT, 2018)

An Energy-Efficient Accelerator with Relative- Indexing Memory for Sparse Compressed Convolutional Neural Network. - I-Chen Wu; Po-Tsang Huang; Chin-Yang Lo; Wei Hwang (AICAS, 2019)

28nm 0.3V 1W2R Sub-Threshold FIFO Memory for Multi-Sensor IoT Applications. - Huan-Jan Tseng; Po-Tsang Huang; Shang-Lin Wu; Sheng-Chi Lung; Wei-Chang Wang; Wei Hwang; Ching-Te Chuang (SoCC, 2019)

Energy-Efficient Accelerator Design with 3D-SRAM and Hierarchical Interconnection Architecture for Compact Sparse CNNs. - Chin-Yang Lo; Po-Tsang Huang; Wei Hwang (AICAS, 2020)

Hierarchical Active Voltage Regulation for Heterogeneous TSV 3D-ICs. - Po-Tsang Huang; Tzung-Han Tsai; Po-Jen Yang; Wei Hwang; Hung-Ming Chen (SoCC, 2020)

An Energy-Efficient Ring-Based CIM Accelerator using High-Linearity eNVM for Deep Neural Networks. - Po-Tsang Huang; Ting-Wei Liu; Wei Lu; Yu-Hsien Lin; Wei Hwang (ISOCC, 2021)

An Energy-Efficient 3D Cross-Ring Accelerator With 3D-SRAM Cubes for Hybrid Deep Neural Networks. - Wei Lu; Po-Tsang Huang; Hung-Ming Chen; Wei Hwang (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

Energy-Efficient Accelerator Design With Tile-Based Row-Independent Compressed Memory for Sparse Compressed Convolutional Neural Networks. - Po-Tsang Huang; I-Chen Wu; Chin-Yang Lo; Wei Hwang (IEEE Open J. Circuits Syst., 2021)

Memory-Centric Fusion-based CNN Accelerator with 3D-NoC and 3D-DRAM. - Wei Lu; Pei-Yu Ge; Po-Tsang Huang; Hung-Ming Chen; Wei Hwang (ISOCC, 2022)