A 230mV 8-bit sub-threshold microprocessor for wireless sensor network. - Wei Jin 004; Sheng Lu; Weifeng He; Zhigang Mao (VLSI-SoC, 2011)

Robust design of sub-threshold flip-flop cells for wireless sensor network. - Wei Jin 004; Sheng Lu; Weifeng He; Zhigang Mao (VLSI-SoC, 2011)

A 0.35V 1.3pJ/cycle 20MHz 8-bit 8-tap FIR core based on wide-pulsed-latch pipelines. - Wei Jin 004; Seongjong Kim; Weifeng He; Zhigang Mao; Mingoo Seok (A-SSCC, 2016)

Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory. - Naifeng Jing; Taozhong Li; Zhongyuan Zhao 004; Wei Jin 004; Yanan Sun 003; Weifeng He; Zhigang Mao (FPT, 2016)

Short path padding with multiple-Vt cells for wide-pulsed-latch based circuits at ultra-low voltage. - Yongming Ding; Wei Jin 004; Guanghui He; Weifeng He (ASICON, 2017)

A 0.2V 2.3pJ/Cycle 28dB output SNR hybrid Markov random field probabilistic-based circuit for noise immunity and energy efficiency. - Xuwei Jin; Wei Jin 004; Hao Zhang 151; Jianfei Jiang 001; Weifeng He (ISCAS, 2017)

A 12-bit 4928 × 3264 pixel CMOS image signal processor for digital still cameras. - Wei Jin 004; Guanghui He; Weifeng He; Zhigang Mao (Integr., 2017)

A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS. - Wei Jin 004; Weifeng He; Jianfei Jiang 001; Haichao Huang; Xuejun Zhao; Yanan Sun 003; Xin Chen; Naifeng Jing (Integr., 2017)

Near- and Sub-Vt Pipelines Based on Wide-Pulsed-Latch Design Techniques. - Wei Jin 004; Seongjong Kim; Weifeng He; Zhigang Mao; Mingoo Seok (IEEE J. Solid State Circuits, 2017)

In Situ Error Detection Techniques in Ultralow Voltage Pipelines: Analysis and Optimizations. - Wei Jin 004; Seongjong Kim; Weifeng He; Zhigang Mao; Mingoo Seok (IEEE Trans. Very Large Scale Integr. Syst., 2017)