Wei Li
Orcid: 0000-0002-6597-0142Affiliations:
- PLA Information Engineering University (Zhengzhou Institute of Information Science and Technology), Department of Microelectronics, Zhengzhou, China
- Fudan University, State Key Lab of ASIC and System, Shanghai, China (PhD 2017)
- PLA Information Engineering University (Zhengzhou Institute of Information Science and Technology), China
According to our database1,
Wei Li
authored at least 22 papers
between 2007 and 2022.
Collaborative distances:
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Bibliography
2022
An energy-efficient reconfigurable asymmetric modular cryptographic operation unit for RSA and ECC.
Frontiers Inf. Technol. Electron. Eng., 2022
A side-channel-attack countermeasure for elliptic curve point multiplication based on dynamic power compensation.
IEICE Electron. Express, 2022
2021
A high-efficient and low-cost secure AMBA framework utilizing configurable data encryption modeling against probe attacks.
IEICE Electron. Express, 2021
An Efficient Module Arithmetic Logic Unit in Dual Field for Internet of Things Applications.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2020
PVHArray: An Energy-Efficient Reconfigurable Cryptographic Logic Array With Intelligent Mapping.
IEEE Trans. Very Large Scale Integr. Syst., 2020
2019
An Efficient ASIC Implementation of Public Key Cryptography Algorithm SM2 Based on Module Arithmetic Logic Unit.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Method for improving energy efficiency of elliptic curve cryptography algorithm on reconfigurable symmetric cipher processor.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Transparent Buffer Management: An Intra-cluster Task Scheduling Method Based on Dynamic Virtual Channel.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
A single-supply sub-threshold level shifter with an internal supply feedback loop for multi-voltage applications.
IEICE Electron. Express, 2018
2017
A highly efficient reconfigurable rotation unit based on an inverse butterfly network.
Frontiers Inf. Technol. Electron. Eng., 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
An area-efficient interconnection network for coarse-grain reconfigurable cryptographic array.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Research of a reconfigurable coarse-grained cryptographic processing unit based on different operation similar structure.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2015
A High-Throughput Processor for Dual-Field Elliptic Curve Cryptography with Power Analysis Resistance.
Proceedings of the 2015 IEEE 12th Intl Conf on Ubiquitous Intelligence and Computing and 2015 IEEE 12th Intl Conf on Autonomic and Trusted Computing and 2015 IEEE 15th Intl Conf on Scalable Computing and Communications and Its Associated Workshops (UIC-ATC-ScalCom), 2015
Fast Parallel Extract-Shift and Parallel Deposit-Shift in General-Purpose Processors.
Proceedings of the 2015 IEEE 12th Intl Conf on Ubiquitous Intelligence and Computing and 2015 IEEE 12th Intl Conf on Autonomic and Trusted Computing and 2015 IEEE 15th Intl Conf on Scalable Computing and Communications and Its Associated Workshops (UIC-ATC-ScalCom), 2015
Study and implementation of cluster hierarchical memory system of multicore cryptographic processor.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2008
Proceedings of the PACIIA 2008, 2008
The Research and Implementation of Reconfigurable Processor Architecture for Block Cipher Processing.
Proceedings of the International Conference on Embedded Software and Systems, 2008
2007
Proceedings of the Advanced Parallel Processing Technologies, 7th International Symposium, 2007