A lab demonstration of a SuperPON optical access network. - Jan Vandewege; Xing-Zhi Qiu; Brecht Stubbe; Chris Coene; Peter Vaes; Wei Li 038; Jan Codenie; Claire Martin; B. Hans Slabbinck; Ingrid Van de Voorde; Paolo Solina; Pietro Obino (Broadband Communications, 1998)

Practical design considerations on lumped element filters for microwave applications. - Wei Li 038; Jan Vandewege (ICECS, 2000)

Low-frequency electronic gate detection for the counting and sizing of cells, bacteria, and colloidal particles in liquids. - Frank De Bisschop; Jan Vandewege; Wei Li 038; Marc De Mets (IEEE Trans. Instrum. Meas., 2003)

A Formal Framework of UML. - Jin Zhou; Yinglong Ma 001; Wei Li 038; Zhilin Wu (Software Engineering Research and Practice, 2004)

An implementation of a CMOS down-conversion mixer for GSM1900 receiver. - Fangqing Chu; Wei Li 038; Junyan Ren (ASP-DAC, 2006)

A Power-Optimized CMOS Quadrature VCO with Wide-Tuning Range for UWB Receivers. - Zhujin Zhou; Ning Li 007; Wei Li 038; Junyan Ren (ISCAS, 2007)

A sideband-suppressed low-power synthesizer for 14-band dual-carrier MB-OFDM UWB transceivers. - Danfeng Chen; Haipeng Fu; Yunfeng Chen; Wei Li 038; Fan Ye 001; Ning Li 007; Junyan Ren (ISCAS, 2010)

A current-mode 6-9GHz UWB transmitter with output power flattening technique. - Yunfeng Chen; Jinhan Fan; Wei Li 038; Ning Li 007; Junyan Ren (ISCAS, 2010)

A fractional-N frequency synthesizer for cellular and short range multi-standard wireless receiver. - Deping Huang; Jin Zhou 001; Wei Li 038; Ning Li 007; Junyan Ren (ISCAS, 2010)

A low-voltage differential injection locked divider with forward body bias. - Haipeng Fu; Hanchao Zhou; Yangyang Niu; Junyan Ren; Wei Li 038; Ning Li 007 (ASICON, 2011)

Low phase noise injection-locked doubler-based quadrature CMOS VCO. - Chen Lian; Wei Li 038; Haipeng Fu; Ning Li 007; Junyan Ren (ASICON, 2011)

A 1.2 V 70 mA low drop-out voltage regulator in 0.13 µm CMOS process. - Qin Wu; Wei Li 038; Ning Li 007; Junyan Ren (ASICON, 2011)

A 80-400 MHz 74 dB-DR Gm-C low-pass filter with a unique auto-tuning system. - Ting Gao; Wei Li 038; Ning Li 007; Junyan Ren (ASP-DAC, 2011)

A 2.1-GHz PLL with -80dBc/-74dBc reference spur based on aperture-phase detector and phase-to-analog converter. - Deyun Cai; Haipeng Fu; Junyan Ren; Wei Li 038; Ning Li 007; Hao Yu 001; Kiat Seng Yeo (A-SSCC, 2011)

A harmonic-suppressed regenerative divide-by-5 frequency divider for UWB applications. - Haipeng Fu; Deyun Cai; Junyan Ren; Wei Li 038 (ISCAS, 2011)

A dual-mode VCO based low-power synthesizer with optimized automatic frequency calibration for software-defined radio. - Jin Zhou 001; Wei Li 038; Deping Huang; Chen Lian; Ning Li 007; Junyan Ren (ISCAS, 2011)

A current-mode RF transmitter for 6-9 GHz MB-OFDM UWB application. - Yunfeng Chen; Jinhan Fan; Wei Li 038; Ning Li 007; Junyan Ren (Sci. China Inf. Sci., 2011)

A 6.2-9.5 GHz receiver for Wimedia MB-OFDM and China UWB standard. - Ting Gao; Feng Zhou; Wei Li 038; Fei Lan; Ning Li 007; Junyan Ren (Sci. China Inf. Sci., 2011)

A 5.5mW 80-400MHz Gm-C low pass filter with a unique auto-tuning system. - Ting Gao; Wei Li 038; Yunfeng Chen; Ning Li 007; Junyan Ren (IEICE Electron. Express, 2011)

A 22-mW 2.2%-EVM UWB Transmitter Using On-Chip Transformer and LO Leakage Calibration. - Yunfeng Chen; Renliang Zheng; Haipeng Fu; Wei Li 038; Ning Li 007; Junyan Ren (IEICE Trans. Electron., 2011)

A Frequency Synthesizer With Optimally Coupled QVCO and Harmonic-Rejection SSBmixer for Multi-Standard Wireless Receiver. - Deping Huang; Wei Li 038; Jin Zhou 001; Ning Li 007; Jinghong Chen (IEEE J. Solid State Circuits, 2011)

A time-to-digital converter based AFC for wideband frequency synthesizer. - Deping Huang; Wei Li 038; Jin Zhou 001; Ning Li 007; Junyan Ren; Jinghong Chen (ISCAS, 2012)

A 2.4GHz to 3.86GHz digitally controlled oscillator with 18.5kHz frequency resolution using single PMOS varactor. - Yangyang Niu; Wei Li 038; Ning Li 007; Junyan Ren (IEICE Electron. Express, 2012)

A 0.13-µm CMOS 0.1-12GHz active balun-LNA for multi-standard applications. - Kaichen Zhang; Wei Li 038; Ning Li 007; Junyan Ren (IEICE Electron. Express, 2013)

A Dividerless PLL With Low Power and Low Reference Spur by Aperture-Phase Detector and Phase-to-Analog Converter. - Deyun Cai; Haipeng Fu; Junyan Ren; Wei Li 038; Ning Li 007; Hao Yu 001; Kiat Seng Yeo (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A 42fJ 8-bit 1.0-GS/s folding and interpolating ADC with 1GHz signal bandwidth. - Mingshuo Wang; Fan Ye 001; Wei Li 038; Junyan Ren (IEICE Electron. Express, 2014)

Algorithms based on all-digital phase-locked loop for fast-locking and spur free. - Wei Xu; Wei Li 038 (ASICON, 2015)

Greedy Approach Based Heuristics for Partitioning Sparse Matrices. - Jiasen Huang; Junyan Ren; Wei Li 038 (IEICE Trans. Inf. Syst., 2015)

A Monolithic Sub-sampling PLL based 6-18 GHz Frequency Synthesizer for C, X, Ku Band Communication. - Hanchao Zhou; Ning Zhu; Wei Li 038; Zibo Zhou; Ning Li 007; Junyan Ren (IEICE Trans. Electron., 2015)

A programmable divider with extended division range for 24GHz FMCW frequency synthesizer. - Yuanyuan Xu; Wei Li 038; Dan Wu; Ning Li 007 (ASICON, 2017)

An Input-Feedforward Delta-Sigma Modulator With Relaxed Timing Constraints. - Qing-Qin Wang; Wei Li 038 (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

An 8-12GHz Class-F3 VCO with Multi-LC Tank in 28nm CMOS. - Tao Wang; Wei Li 038; Haoyang Zhou; Jiao Ye; Yuanyuan Xu (ASICON, 2019)

A Class-F3 VCO with 104% Ultra-Wide Band Tuning Range and -125dBc/Hz Phase Noise. - Haoyang Zhou; Wei Li 038; Tao Wang; Jiao Ye; Chuangguo Wang (ASICON, 2019)

A 65 nm 19.1-to-20.4 GHz Sigma-Delta Fractional-N Frequency Synthesizer with Two-Point Modulation for FMCW Radar Applications. - Yuanyuan Xu; Wei Li 038; Wei Wang; Dan Wu; Lai He; Jintao Hu (IEICE Trans. Electron., 2019)

A 0.5-to-3GHz Full-Duplex Receiver with 27dB Self-Interference-Cancellation. - Chuangguo Wang; Wei Li 038; Tao Wang; Lai He (ISCAS, 2020)

A 0.9V 0.1-4GHz LNTA in 28-nm CMOS Achieving +11.3dBm IIP3 With Self-loaded Linearization Technique. - Fan Chen; Wei Li 038; Chuangguo Wang; Hongtao Xu (ASICON, 2021)

Design of A Reference Buffer with Ultralow Output Resistance for High-speed ADCs. - Bingbing Ma; Longbo Fan; Wei Li 038; Hongtao Xu (ASICON, 2021)

A 0.2 3.8-GHz Full-Duplex Receiver With More Than 25 dB Self-Interference Cancellation Using a C-DAC-Based Vector Canceller. - Chuangguo Wang; Wei Li 038; Hongtao Xu (IEEE Access, 2021)

A 4.7-to-18-GHz Ultra-Wideband Variable-Gain Balun-LNA Using 3rd-Order-Band-Pass Input Matching in 40-nm CMOS. - Sicheng Han; Xueyin Wu; Wei Li 038; Yun Wang 008; Yue Lin 009; Hongtao Xu (ASICON, 2023)

A Compact 144% Fractional Bandwidth CMOS Power Amplifier With an Optimization of Synthesized High-Order Matching Network. - Yunhao Li; Wei Li 038; Yun Wang 008; Wei Luo; Yue Lin 009; Hongtao Xu (ASICON, 2023)

A 115-325MHz Wideband Analog Baseband with 0.5dB-Step Variable Gain Amplifier and Six-order Reconfigurable Gm-C Lowpass Filter. - Wen Zuo; Wei Li 038; Yun Wang 008; Yue Lin 009; Hongtao Xu (ASICON, 2023)

A 12.1-16.5GHz Resistance Self-biased Inverse Class-F23 VCO Achieving 20-54kHz 1/f3 Corner Frequency. - Jiayu Jing; Wei Li 038; Ren Yuan; Hongtao Xu (ISCAS, 2023)

A 0.7-to-2.5GHz Sliding Digital-IF Quadrature Digital Transmitter Achieving >40% System Efficiency for Multi-Mode NB-IoT/BLE Applications. - Chunxiao Hu; Diyang Zheng; Yun Yin; Jie Lin; Yicheng Li 002; Wei Li 038; Hongtao Xu (ISSCC, 2023)

A Tri-Mode Reconfigurable Receiver for GNSS/NB-IoT/BLE With 68-dB HR3 and 60-dB IMRR in 28-nm CMOS. - Yunyou Pu; Wei Li 038; Mengqi Li; Chuangguo Wang; Fan Chen; Qiaoan Li; Hongtao Xu (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A 140-Gbps 1-to-21-GHz Ultra-Wideband LNA Achieving 1.95-to-3-dB NF Using Gm-Assisted-Feedback Noise Suppression Technique in 40nm Bulk CMOS. - Sicheng Han; Yun Wang 008; Yunhao Li; Wen Zuo; Wei Li 038; Yue Lin 009; Hongtao Xu (VLSI Technology and Circuits, 2024)

A Wideband Sliding Digital-IF Quadrature Digital Transmitter for Multimode NB-IoT/BLE Applications. - Chunxiao Hu; Diyang Zheng; Yun Yin; Jie Lin; Yicheng Li 002; Wei Li 038; Hongtao Xu (IEEE J. Solid State Circuits, 2024)

A Wideband Full-Duplex Receiver With Multi-Domain Self-Interference Cancellation Based on Capacitor Stacking Delay and Delay Compensation in Cancellers. - Chuangguo Wang; Xingyu Ma; Wei Li 038; Fan Chen; Wen Zuo; Yunyou Pu; Jin Zhou 001; Hongtao Xu (IEEE J. Solid State Circuits, 2024)

Analysis and Calibration of Bit Weights in SAR and Pipelined SAR ADCs Based on Code Distribution. - Bingbing Ma; Wei Li 038; Hongtao Xu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Enhanced-Linearity Wideband Full-Duplex Receiver With Shared Self-Interference Canceller. - Fan Chen; Wei Li 038; Chuangguo Wang; Yunyou Pu; Xingyu Ma; Shijiao Dong; Yun Wang 008; Hongtao Xu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A Compact Full-Duplex Receiver with Wideband Multi-Domain Hilbert-Transform-Equalization Cancellation Based on Multi-Stage APFs Achieving 65dB SIC Across 120MHz BW. - Xingyu Ma; Wei Li 038; Shijiao Dong; Ruiyu Lyu; Fan Chen; Yunyou Pu; Chuangguo Wang; Hongtao Xu (ISSCC, 2025)

A 1-21-GHz, 1.95-3.1-dB NF Ultra-Wideband LNA With Gₘ-Assisted-Feedback Noise Suppression Achieving 140-Gb/s Data Rate in 40-nm CMOS. - Sicheng Han; Yun Wang 008; Yunhao Li; Wen Zuo; Wei Li 038; Yun Yin; Yue Lin 009; Hongtao Xu (IEEE J. Solid State Circuits, 2025)

A 2.4-GHz-BW 59.7-dB-Range 0.39-dB-Error dB-Linear VGA Featuring -40 °C 110 °C and ±10%-Supply PVT Robustness in 40-Nm CMOS. - Wen Zuo; Yun Wang 008; Sicheng Han; Yunhao Li; Wei Li 038; Yue Lin 009; Hongtao Xu (IEEE J. Solid State Circuits, 2025)