Design and Implementation of a High-Speed Reconfigurable Modular Arithmetic Unit. - Wei Li 131; Zibin Dai; Tao Chen 047; Tao Meng; Xuan S. Yang (APPT, 2007)

The Research and Implementation of Reconfigurable Processor Architecture for Block Cipher Processing. - Zibin Dai; Wei Li 131; Xiaohui Yang; Tao Chen 047; Qiao Ren (ICESS, 2008)

Research and Implementation of a High-Speed Reconfigurable A5 Algorithm. - Wei Li 131; Zibin Dai; Longmei Nan (PACIIA (2), 2008)

Design and application of reusable SoC verification platform. - Lulu Feng; Zibin Dai; Wei Li 131; Jianlei Cheng (ASICON, 2011)

Research on design of a reconfigurable parallel structure targeted at LFSR. - Wei Li 131; Xuan Yang; Zibin Dai (ASICON, 2011)

Study and implementation of cluster hierarchical memory system of multicore cryptographic processor. - Junwei Li; Zibin Dai; Wei Li 131; Tao Chen 047; Yufei Zhu (ASICON, 2015)

Fast Parallel Extract-Shift and Parallel Deposit-Shift in General-Purpose Processors. - Wei Li 131; Zhongxiang Chang; Xiao Feng; Zibin Dai (UIC/ATC/ScalCom, 2015)

A High-Throughput Processor for Dual-Field Elliptic Curve Cryptography with Power Analysis Resistance. - Wei Li 131; Xiaoyang Zeng; Xiao Feng; Zibin Dai (UIC/ATC/ScalCom, 2015)

Research of a reconfigurable coarse-grained cryptographic processing unit based on different operation similar structure. - Longmei Nan; Xiaoyang Zeng; Zhouchuang Wang; Yiran Du; Wei Li 131 (ASICON, 2017)

An area-efficient interconnection network for coarse-grain reconfigurable cryptographic array. - Tongzhou Qu; Zibin Dai; Longmei Nan; Wei Li 131; Anqi Yin (ASICON, 2017)

RC6 architecture-adaptive implementation for coarse-grained reconfiguration array. - Anqi Yin; Zibin Dai; Longmei Nan; Wei Li 131 (ASICON, 2017)

A highly efficient reconfigurable rotation unit based on an inverse butterfly network. - Chao Ma; Zibin Dai; Wei Li 131; Hai-juan Zang (Frontiers Inf. Technol. Electron. Eng., 2017)

A single-supply sub-threshold level shifter with an internal supply feedback loop for multi-voltage applications. - Longmei Nan; Xiaoyang Zeng; Wei Li 131; Zhouchuang Wang; Zibin Dai (IEICE Electron. Express, 2018)

Transparent Buffer Management: An Intra-cluster Task Scheduling Method Based on Dynamic Virtual Channel. - Guangqiu Lv; Wei Li 131; Tao Chen 047; Longmei Nan (ASICON, 2019)

Method for improving energy efficiency of elliptic curve cryptography algorithm on reconfigurable symmetric cipher processor. - Zhao Tuo; Tao Chen 047; Wei Li 131; Danyang Yang (ASICON, 2019)

An Efficient ASIC Implementation of Public Key Cryptography Algorithm SM2 Based on Module Arithmetic Logic Unit. - Danyang Yang; Zibin Dai; Wei Li 131; Tao Chen 047 (ASICON, 2019)

PVHArray: An Energy-Efficient Reconfigurable Cryptographic Logic Array With Intelligent Mapping. - Yiran Du; Wei Li 131; Zibin Dai; Longmei Nan (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Effective Register Allocation for Configurable VLIW Crypto-Processor. - Aiqing Wu; Mengni Bie; Longmei Nan; Wei Li 131 (ASICON, 2021)

An Efficient Module Arithmetic Logic Unit in Dual Field for Internet of Things Applications. - Han Zeng; Wei Li 131; Tao Chen 047; Longmei Nan (ASICON, 2021)

A high-efficient and low-cost secure AMBA framework utilizing configurable data encryption modeling against probe attacks. - Kai Wang; Wei Li 131; Yanjiang Liu; Tao Chen 047; Longmei Nan; Xianzhao Xia (IEICE Electron. Express, 2021)

A side-channel-attack countermeasure for elliptic curve point multiplication based on dynamic power compensation. - Wei Li 131; Han Zeng; Tao Chen 047; Longmei Nan; Chenguang Yang 007 (IEICE Electron. Express, 2022)

An energy-efficient reconfigurable asymmetric modular cryptographic operation unit for RSA and ECC. - Mengni Bie; Wei Li 131; Tao Chen 047; Longmei Nan; Danyang Yang (Frontiers Inf. Technol. Electron. Eng., 2022)

A Domain-Specific DMA Structure for Per-channel Processing-based CNN Accelerator. - Yi Chen; Tao Chen 047; Mengni Bie; Longmei Nan; Wei Li 131; Yiran Du (ASICON, 2023)