Power dissipation in division. - Wei Liu 016; Alberto Nannarelli (ACSCC, 2008)

On-chip Thermal Modeling Based on SPICE Simulation. - Wei Liu 016; Andrea Calimera; Alberto Nannarelli; Enrico Macii; Massimo Poncino (PATMOS, 2009)

Power dissipation challenges in multicore floating-point units. - Wei Liu 016; Alberto Nannarelli (ASAP, 2010)

Post-placement temperature reduction techniques. - Wei Liu 016; Alberto Nannarelli; Andrea Calimera; Enrico Macii; Massimo Poncino (DATE, 2010)

Temperature dependent wire delay estimation in floorplanning. - Andreas Thor Winther; Wei Liu 016; Alberto Nannarelli; Sarma B. K. Vrudhula (NORCHIP, 2011)

NBTI effects on tree-like clock distribution networks. - Wei Liu 016; Sandeep Miryala; Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2012)

Power Efficient Division and Square Root Unit. - Wei Liu 016; Alberto Nannarelli (IEEE Trans. Computers, 2012)

Modeling and characterization of thermally induced skew on clock distribution networks of nanometric ICs. - Alessandro Sassone; Wei Liu 016; Andrea Calimera; Alberto Macii; Enrico Macii; Massimo Poncino (Microelectron. J., 2013)

Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization. - Wei Liu 016; Andrea Calimera; Alberto Macii; Enrico Macii; Alberto Nannarelli; Massimo Poncino (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Thermal aware floorplanning incorporating temperature dependent wire delay estimation. - Andreas Thor Winther; Wei Liu 016; Alberto Nannarelli; Sarma B. K. Vrudhula (Microprocess. Microsystems, 2015)

Power and Thermal Efficient Numerical Processing. - Wei Liu 016; Alberto Nannarelli (Handbook on Data Centers, 2015)