Bit-Cost-Scalable 3D DRAM Architecture and Unit Cell First Demonstrated with Integrated Gate-Around and Channel-Around IGZO FETs. - Feng-Min Lee; Po-Hao Tseng; Yu-Yu Lin; Yu-Hsuan Lin; Wei-Lun Weng; Nei-Chih Lin; Po-Jung Sung; Chien-Ting Wu; Chih-Chao Yang; Wen-Fa Wu; Chang-Hong Shen; Tuo-Hung Hou; et al. (VLSI Technology and Circuits, 2024)