Memristor-Based Phase-Lead Controller Circuit Design. - Tsung-Chih Lin; Wei-Nan Liao; Valentina Emilia Balas (SOFA, 2012)

A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. - Chi-Shin Chang; Hao-I Yang; Wei-Nan Liao; Yi-Wei Lin; Nan-Chun Lien; Chien-Hen Chen; Ching-Te Chuang; Wei Hwang; Shyh-Jye Jou; Ming-Hsien Tu; Huan-Shun Huang; Yong-Jyun Hu; et al. (ISCAS, 2013)

A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control. - Wei-Nan Liao; Nan-Chun Lien; Chi-Shin Chang; Li-Wei Chu; Hao-I Yang; Ching-Te Chuang; Shyh-Jye Jou; Wei Hwang; Ming-Hsien Tu; Huan-Shun Huang; Jian-Hao Wang; Paul-Sen Kan; et al. (SoCC, 2013)

A 70.85-86.27TOPS/W PVT-Insensitive 8b Word-Wise ACIM with Post-Processing Relaxation. - Sung-En Hsieh; Chun-Hao Wei; Cheng-Xin Xue; Hung-Wei Lin; Wei-Hsuan Tu; En-Jui Chang; Kai-Taing Yang; Po-Heng Chen; Wei-Nan Liao; Li Lian Low; Chia-Da Lee; Allen-Cl Lu; et al. (ISSCC, 2023)