A high-throughput, low power architecture and its VLSI implementation for DFT/IDFT computation. - Shen-Fu Hsiao; Wei-Ren Shiue (ICASSP, 1999)

New hardware-efficient algorithm and architecture for the computation of 2-D DCT on a linear systolic array. - Shen-Fu Hsiao; Wei-Ren Shiue (ICASSP, 1999)

A cost-efficient and fully-pipelinable architecture for DCT/IDCT. - Shen-Fu Hsiao; Wei-Ren Shiue; Jian-Ming Tseng (IEEE Trans. Consumer Electron., 1999)

Low-cost unified architectures for the computation of discrete trigonometric transforms. - Shen-Fu Hsiao; Wei-Ren Shiue (ICASSP, 2000)

A new hardware-efficient algorithm and architecture for computation of 2-D DCTs on a linear array. - Shen-Fu Hsiao; Wei-Ren Shiue (IEEE Trans. Circuits Syst. Video Technol., 2001)