A 0.01mm2 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor. - Linxiao Shen; Yi Shen 007; Xiyuan Tang; Chen-Kai Hsu; Wei Shi 011; Shaolan Li; Wenda Zhao; Abhishek Mukherjee; Nan Sun 001 (ISSCC, 2019)

An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier. - Xiyuan Tang; Begum Kasap; Linxiao Shen; Xiangxing Yang; Wei Shi 011; Nan Sun 001 (VLSI Circuits, 2019)

A Two-Step ADC With a Continuous-Time SAR-Based First Stage. - Linxiao Shen; Nan Sun 001; Yi Shen 007; Zhelu Li; Wei Shi 011; Xiyuan Tang; Shaolan Li; Wenda Zhao; Mantian Zhang; Zhangming Zhu (IEEE J. Solid State Circuits, 2019)

Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis. - Mingjie Liu; Keren Zhu 001; Xiyuan Tang; Biying Xu; Wei Shi 011; Nan Sun 001; David Z. Pan (DAC, 2020)

9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier. - Xiyuan Tang; Xiangxing Yang; Wenda Zhao; Chen-Kai Hsu; Jiaxin Liu; Linxiao Shen; Abhishek Mukherjee; Wei Shi 011; David Z. Pan; Nan Sun 001 (ISSCC, 2020)

An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier. - Xiyuan Tang; Linxiao Shen; Begum Kasap; Xiangxing Yang; Wei Shi 011; Abhishek Mukherjee; David Z. Pan; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier. - Xiyuan Tang; Xiangxing Yang; Wenda Zhao; Chen-Kai Hsu; Jiaxin Liu; Linxiao Shen; Abhishek Mukherjee; Wei Shi 011; Shaolan Li; David Z. Pan; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

A 79dB-SNDR 167dB-FoM Bandpass ΔΣ ADC Combining N-Path Filter with Noise-Shaping SAR. - Linxiao Shen; Zijie Gao; Xiangxing Yang; Wei Shi 011; Nan Sun 001 (ISSCC, 2021)

10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR. - Wei Shi 011; Jiaxin Liu; Abhishek Mukherjee; Xiangxing Yang; Xiyuan Tang; Linxiao Shen; Wenda Zhao; Nan Sun 001 (ISSCC, 2021)

A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier. - Xiyuan Tang; Xiangxing Yang; Jiaxin Liu; Wei Shi 011; David Z. Pan; Nan Sun 001 (ISSCC, 2021)

Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits. - Keren Zhu 001; Hao Chen 059; Mingjie Liu; Xiyuan Tang; Wei Shi 011; Nan Sun 001; David Z. Pan (ASP-DAC, 2022)

A 0.37mm2 250kHz-BW 95dB-SNDR CTDSM with Low-Cost 2nd-order Vector-Quantizer DEM. - Wei Shi 011; Xing Wang; Xiyuan Tang; Abhishek Mukherjee; Raviteja Theertham; Shanthi Pavan; Lu Jie 001; Nan Sun 001 (CICC, 2022)

RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL. - Wei Shi 011; Hanrui Wang 002; Jiaqi Gu 002; Mingjie Liu; David Z. Pan; Song Han 003; Nan Sun 001 (MLCAD, 2022)

An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization. - Ahmet Faruk Budak; Miguel Gandara; Wei Shi 011; David Z. Pan; Nan Sun 001; Bo Liu 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Wireless Implantable Opto-Electro Neural Interface ASIC for Simultaneous Neural Recording and Stimulation. - Linran Zhao; Yan Gong; Wei Shi 011; Raymond Stephany; Wen Li 004; Yaoyao Jia (CICC, 2023)

A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier. - Xiyuan Tang; Xiangxing Yang; Jiaxin Liu; Zongnan Wang; Wei Shi 011; David Z. Pan; Nan Sun 001 (IEEE J. Solid State Circuits, 2023)

Ads Supply Personalization via Doubly Robust Learning. - Wei Shi 011; Chen Fu; Qi Xu; Sanjian Chen; Jizhe Zhang; Qinqin Zhu; Zhigang Hua; Shuang Yang (CIKM, 2024)

PVTSizing: A TuRBO-RL-Based Batch-Sampling Optimization Framework for PVT-Robust Analog Circuit Synthesis. - Zichen Kong; Xiyuan Tang; Wei Shi 011; Yiheng Du; Yibo Lin; Yuan Wang 001 (DAC, 2024)

33.9 A Miniature Neural Interface Implant with a 95% Charging Efficiency Optical Stimulator and an 81.9dB SNDR ΔΣM-Based Recording Frontend. - Linran Zhao; Wei Shi 011; Yan Gong; Xiang Liu; Wen Li 004; Yaoyao Jia (ISSCC, 2024)

Session-Level Dynamic Ad Load Optimization using Offline Robust Reinforcement Learning. - Tao Liu 035; Qi Xu; Wei Shi 011; Zhigang Hua; Shuang Yang (KDD (1), 2025)

An Energy-Efficient and Artifact-Resilient ASIC for Simultaneous Neural Recording and Optogenetic Stimulation. - Linran Zhao; Yan Gong; Raymond G. Stephany; Wei Shi 011; Wen Li 004; Yaoyao Jia (IEEE Trans. Biomed. Circuits Syst., 2025)