Building asynchronous routers with independent sub-channels. - Wei Song 002; Doug A. Edwards (SoC, 2009)

Adaptive stochastic routing in fault-tolerant on-chip networks. - Wei Song 002; Doug A. Edwards; José Luis Núñez-Yáñez; Sohini Dasgupta (NOCS, 2009)

An Asynchronous Routing Algorithm for Clos Networks. - Wei Song 002; Doug A. Edwards (ACSD, 2010)

A low latency wormhole router for asynchronous on-chip networks. - Wei Song 002; Doug A. Edwards (ASP-DAC, 2010)

Routing of asynchronous Clos networks. - Wei Song 002; D. Edwards; Z. Liu; S. Dasgupta (IET Comput. Digit. Tech., 2011)

Asynchronous spatial division multiplexing router. - Wei Song 002; Doug A. Edwards (Microprocess. Microsystems, 2011)

Area efficient asynchronous SDM routers using 2-stage Clos switches. - Wei Song 002; Doug A. Edwards; Jim D. Garside; William J. Bainbridge (DATE, 2012)

Automatic Controller Detection for Large Scale RTL Designs. - Wei Song 002; Jim D. Garside (DSD, 2013)

Transient Fault Tolerant QDI Interconnects Using Redundant Check Code. - Guangda Zhang; Wei Song 002; Jim D. Garside; Javier Navaridas; Zhiying Wang 003 (DSD, 2013)

An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults. - Guangda Zhang; Wei Song 002; Jim D. Garside; Javier Navaridas; Zhiying Wang 003 (ASYNC, 2014)

An empirical evaluation of High-Level Synthesis languages and tools for database acceleration. - Oriol Arcas-Abella; Geoffrey Ndu; Nehir Sönmez; Mohsen Ghasempour; Adrià Armejach; Javier Navaridas; Wei Song 002; John Mawer; Adrián Cristal; Mikel Luján (FPL, 2014)

On-line detection of the deadlocks caused by permanently faulty links in quasi-delay insensitive networks on chip. - Wei Song 002; Guangda Zhang; Jim D. Garside (ACM Great Lakes Symposium on VLSI, 2014)

Automatic data path extraction in large-scale register-transfer level designs. - Wei Song 002; Jim D. Garside; Doug A. Edwards (ISCAS, 2014)

Protecting QDI interconnects from transient faults using delay-insensitive redundant check codes. - Guangda Zhang; Wei Song 002; Jim D. Garside; Javier Navaridas; Zhiying Wang 003 (Microprocess. Microsystems, 2014)

Deadlock Recovery in Asynchronous Networks on Chip in the Presence of Transient Faults. - Guangda Zhang; Jim D. Garside; Wei Song 002; Javier Navaridas; Zhiying Wang 003 (ASYNC, 2015)

Parallel Hardware Merge Sorter. - Wei Song 002; Dirk Koch; Mikel Luján; Jim D. Garside (FCCM, 2016)

Handling Physical-Layer Deadlock Caused by Permanent Faults in Quasi-Delay-Insensitive Networks-on-Chip. - Guangda Zhang; Wei Song 002; Jim D. Garside; Javier Navaridas; Zhiying Wang 003 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Stateful Forward-Edge CFI Enforcement with Intel MPX. - Jun Zhang; Rui Hou 001; Wei Song 002; Zhiyuan Zhan; Boyan Zhao; Mingyu Chen 001; Dan Meng 002 (ACA, 2018)

Dynamically Finding Minimal Eviction Sets Can Be Quicker Than You Think for Side-Channel Attacks against the LLC. - Wei Song 002; Peng Liu 005 (RAID, 2019)

RAGuard: An Efficient and User-Transparent Hardware Mechanism against ROP Attacks. - Jun Zhang; Rui Hou 001; Wei Song 002; Sally A. McKee; Zhen Jia 001; Chen Zheng 001; Mingyu Chen 001; Lixin Zhang 002; Dan Meng 002 (ACM Trans. Archit. Code Optim., 2019)

Randomized Last-Level Caches Are Still Vulnerable to Cache Side-Channel Attacks! But We Can Fix It. - Wei Song 002; Boya Li; Zihan Xue; Zhenzhen Li; Wenhao Wang 001; Peng Liu 005 (SP, 2021)

A Comprehensive and Cross-Platform Test Suite for Memory Safety - Towards an Open Framework for Testing Processor Hardware Supported Security Extensions. - Wei Song 002; Jiameng Ying; Sihao Shen; Boya Li; Hao Ma; Peng Liu 005 (CoRR, 2021)

Methods of Extracting Parameters of the Processor Caches. - Sihao Shen; Zhenzhen Li; Wei Song 002 (IWSEC, 2022)

Remapped Cache Layout: Thwarting Cache-Based Side-Channel Attacks with a Hardware Defense. - Wei Song 002; Rui Hou 001; Peng Liu 005; Xiaoxin Li; Peinan Li; Lutan Zhao; Xiaofei Fu; Yifei Sun; Dan Meng 002 (CoRR, 2022)

CTPP: A Fast and Stealth Algorithm for Searching Eviction Sets on Intel Processors. - Zihan Xue; Jinchi Han; Wei Song 002 (RAID, 2023)

The Early Bird Catches the Leak: Unveiling Timing Side Channels in LLM Serving Systems. - Linke Song; Zixuan Pang; Wenhao Wang 001; Zihao Wang; XiaoFeng Wang 001; Hongbo Chen; Wei Song 002; Yier Jin; Dan Meng 002; Rui Hou 001 (CoRR, 2024)

Randomizing Set-Associative Caches Against Conflict-Based Cache Side-Channel Attacks. - Wei Song 002; Zihan Xue; Jinchi Han; Zhenzhen Li; Peng Liu 005 (IEEE Trans. Computers, 2024)

WhistleBlower: A System-Level Empirical Study on RowHammer. - Wei He; Zhi Zhang 001; Yueqiang Cheng; Wenhao Wang 001; Wei Song 002; Yansong Gao 001; Qifei Zhang 001; Kang Li; Dongxi Liu; Surya Nepal (IEEE Trans. Computers, 2025)