18.7 A 2.4mm2 130mW MMSE-nonbinary-LDPC iterative detector-decoder for 4×4 256-QAM MIMO in 65nm CMOS. - Chia-Hsiang Chen; Wei Tang 010; Zhengya Zhang (ISSCC, 2015)

A 0.58mm2 2.76Gb/s 79.8pJ/b 256-QAM massive MIMO message-passing detector. - Wei Tang 010; Chia-Hsiang Chen; Zhengya Zhang (VLSI Circuits, 2016)

LEIA: A 2.05mm2 140mW lattice encryption instruction accelerator in 40nm CMOS. - Shiming Song 002; Wei Tang 010; Thomas Chen 003; Zhengya Zhang (CICC, 2018)

A 1.8Gb/s 70.6pJ/b 128×16 link-adaptive near-optimal massive MIMO detector in 28nm UTBB-FDSOI. - Wei Tang 010; Hemanth Prabhu; Liang Liu 002; Viktor Öwall; Zhengya Zhang (ISSCC, 2018)

CASCADE: Connecting RRAMs to Extend Analog Dataflow In An End-To-End In-Memory Processing Paradigm. - Teyuh Chou; Wei Tang 010; Jacob Botimer; Zhengya Zhang (MICRO, 2019)

A 2.4-mm2 130-mW MMSE-Nonbinary LDPC Iterative Detector Decoder for 4×4 256-QAM MIMO in 65-nm CMOS. - Wei Tang 010; Chia-Hsiang Chen; Zhengya Zhang (IEEE J. Solid State Circuits, 2019)

PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA. - Sung-Gun Cho; Wei Tang 010; Chester Liu; Zhengya Zhang (VLSI Circuits, 2021)

VOTA: A 2.45TFLOPS/W Heterogeneous Multi-Core Visual Object Tracking Accelerator Based on Correlation Filters. - Junkang Zhu; Wei Tang 010; Ching-En Lee; Haolei Ye; Eric McCreath; Zhengya Zhang (VLSI Circuits, 2021)

A 0.58-mm2 2.76-Gb/s 79.8-pJ/b 256-QAM Message-Passing Detector for a 128 × 32 Massive MIMO Uplink System. - Wei Tang 010; Chia-Hsiang Chen; Zhengya Zhang (IEEE J. Solid State Circuits, 2021)

NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level Packaging. - Teyuh Chou; Wei Tang 010; Mihai D. Rotaru; Chester Liu; Rahul Dutta; Sharon Lim Pei Siang; David Ho Soon Wee; Surya Bhattacharya; Zhengya Zhang (VLSI Technology and Circuits, 2022)

An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine. - Justin M. Correll; Lu Jie 001; Seungheun Song; Seungjong Lee; Junkang Zhu; Wei Tang 010; Luke Wormald; Jack Erhardt; Nicolas Breil; Roger Quon; Deepak Kamalanathan; Siddarth A. Krishnan; et al. (VLSI Technology and Circuits, 2022)

VOTA: A Heterogeneous Multicore Visual Object Tracking Accelerator Using Correlation Filters. - Junkang Zhu; Wei Tang 010; Ching-En Lee; Haolei Ye; Eric McCreath; Zhengya Zhang (IEEE J. Solid State Circuits, 2022)

Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 Interface to Provide Versatile Workload Acceleration. - Wei Tang 010; Sung-Gun Cho; Tim Tri Hoang; Jacob Botimer; Wei Qiang Zhu; Ching-Chi Chang; Cheng-Hsun Lu; Junkang Zhu; Yaoyu Tao; Tianyu Wei; Naomi Kavi Motwani; Mani Yalamanchi; et al. (VLSI Technology and Circuits, 2023)

Design Approach for Die-to-Die Interfaces to Enable Energy-Efficient Chiplet Systems. - Vikram Jain; Wei Tang 010; Zuoguo Wu; Viansa Schmulbach; Yakun Sophia Shao; Zhengya Zhang; Borivoje Nikolic (ISLPED, 2024)

Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration. - Wei Tang 010; Sung-Gun Cho; Tim Tri Hoang; Jacob Botimer; Wei Qiang Zhu; Ching-Chi Chang; Cheng-Hsun Lu; Junkang Zhu; Yaoyu Tao; Tianyu Wei; Naomi Kavi Motwani; Mani Yalamanchi; et al. (IEEE J. Solid State Circuits, 2024)

25.1 A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100% Solvability and 31.7μs Solution Time. - Evangelos Dikopoulos; Ying-Tuan Hsu; Luke Wormald; Wei Tang 010; Zhengya Zhang; Michael P. Flynn (ISSCC, 2025)

Energy-Efficient Parallel Interconnects for Chiplet Integration. - Wei Tang 010; Chester Liu; Zhengya Zhang (IEEE Micro, 2025)

RXO-LDPC: A Physics-Inspired Relaxation Oscillator-Based Solver Leveraging Six-Body Spin Interactions for Soft Decoding of LDPC Codes. - Evangelos Dikopoulos; Luke Wormald; Ying-Tuan Hsu; Wei Tang 010; Po-Shao Chen; Zhengya Zhang; Michael P. Flynn (IEEE J. Solid State Circuits, 2025)

An 8-bit 20.7 TOPS/W Multilevel Cell ReRAM Macro With ADC-Assisted Bit-Serial Processing. - Justin M. Correll; Lu Jie 001; Seungheun Song; Seungjong Lee; Junkang Zhu; Wei Tang 010; Luke Wormald; Jack Erhardt; Nicolas Breil; Roger Quon; Deepak Kamalanathan; Siddarth A. Krishnan; et al. (IEEE J. Solid State Circuits, 2025)