Fast and Accurate Interval-Based Timing Estimator for Variability-Aware FPGA Physical Synthesis Tools. - Chee Sing Lee 002; Wei Ting Loke; Wenjuan Zhang; Yajun Ha (FPL, 2007)

A Routing Architecture for FPGAs with Dual-VT Switch Box and Logic Clusters. - Wei Ting Loke; Yajun Ha (ARC, 2012)

Power-aware FPGA technology mapping for programmable-VT architectures (abstract only). - Wei Ting Loke; Yajun Ha (FPGA, 2012)

A Power and Cluster-Aware Technology Mapping and Clustering Scheme for Dual-VT FPGAs. - Wei Ting Loke; Yajun Ha; Wenfeng Zhao (IPDPS Workshops, 2012)

Criticality-based routing for FPGAS with reverse body bias switch box architectures. - Wei Ting Loke; Wenfeng Zhao; Yajun Ha (FPL, 2013)

Energy-aware scheduling for task adaptive FPGAs. - Wei Ting Loke; Chin Yang Koay (FPT, 2016)

An Energy-Efficient Design-Time Scheduler for FPGAs Leveraging Dynamic Frequency Scaling Emulation (Abstract Only). - Wei Ting Loke; Chin Yang Koay (FPGA, 2017)