A Temporal Assertion Extension to Verilog. - Kai-Hui Chang; Wei-Ting Tu; Yi-Jong Yeh; Sy-Yen Kuo (ATVA, 2004)

Automatic Partitioner for Behavior Level Distributed Logic Simulation. - Kai-Hui Chang; Jeh-Yen Kang; Han-Wei Wang; Wei-Ting Tu; Yi-Jong Yeh; Sy-Yen Kuo (FORTE, 2005)

A Secure Quantum Communication Protocol Using Insecure Public Channels. - I-Ming Tsai; Chia-Mu Yu; Wei-Ting Tu; Sy-Yen Kuo (SEC, 2005)

Current path analysis for electrostatic discharge protection. - Hung-Yi Liu; Chung-Wei Lin; Szu-Jui Chou; Wei-Ting Tu; Chih-Hung Liu 001; Yao-Wen Chang; Sy-Yen Kuo (ICCAD, 2006)

Accurate Estimation of Buffered Interconnect Delay Based on Virtual Buffering and Multi-Level Cluster Tree Techniques. - Chen-Ho Chen; Chien-Nan Jimmy Liu; Wei-Ting Tu; Tung-Chieh Chen; Iris Hui-Ru Jiang (APCCAS, 2024)