A CMOS low-voltage fully differential sample-and-hold circuit. - Chi-Chang Lu; Wei-Xiang Tung; Chien-Kuo Huang (APCCAS, 2008)

A 1.5V 12-b 40 MSamples/s CMOS pipelined ADC. - Chi-Chang Lu; Wei-Xiang Tung (ISCAS, 2010)