A 2 V 1.6 GHz BJT phase-locked loop. - Wei-Zen Chen; Jieh-Tsorng Wu (CICC, 1998)

A 2-V 2-GHz BJT variable frequency oscillator. - Wei-Zen Chen; Jieh-Tsorng Wu (IEEE J. Solid State Circuits, 1998)

A 2-V, 1.8-GHz BJT phase-locked loop. - Wei-Zen Chen; Jieh-Tsorng Wu (IEEE J. Solid State Circuits, 1999)

A 2.5 Gbps CMOS optical receiver analog front-end. - Wei-Zen Chen; Chao-Hsin Lu (CICC, 2002)

10 GHz quadrature-phase voltage controlled oscillator and prescaler. - Wei-Zen Chen; Chien-Liang Kuo; Chia-Chun Liu (ESSCIRC, 2003)

A 1.8 V, 10 Gbps fully integrated CMOS optical receiver analog front end. - Wei-Zen Chen; Ying-Lien Cheng (ESSCIRC, 2004)

A 2-V 2.3/4.6-GHz dual-band frequency synthesizer in 0.35-μm digital CMOS process. - Wei-Zen Chen; Jia-Xian Chang; Ying-Jen Hong; Meng-Tzer Wong; Chien-Liang Kuo (IEEE J. Solid State Circuits, 2004)

Miniaturized 3-dimensional transformer design. - Wei-Zen Chen; Kuo-Ching Hsu (CICC, 2005)

A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end. - Wei-Zen Chen; Ying-Lien Cheng; Da-Shin Lin (IEEE J. Solid State Circuits, 2005)

A low power programmable PRBS generator and a clock multiplier unit for 10 Gbps serdes applications. - Wei-Zen Chen; Guan-Sheng Huang (ISCAS, 2006)

Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-μm digital CMOS technology. - Wei-Zen Chen; Chao-Hsin Lu (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

A 2.5 Gbps CMOS Fully Integrated Optical Receicer with Lateral PIN Detector. - Wei-Zen Chen; Shih-Hao Huang (CICC, 2007)

Three-Dimensional Fully Symmetric Inductors, Transformer, and Balun in CMOS Technology. - Wei-Zen Chen; Wen-Hui Chen; Kuo-Ching Hsu (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

A 90-dB Omega 10-Gb/s Optical Receiver Analog Front-End in a 0.18µm CMOS Technology. - Wei-Zen Chen; Da-Shin Lin (IEEE Trans. Very Large Scale Integr. Syst., 2007)

A 3-to-10GHz 14-Band CMOS Frequency Synthesizer with Spurs Reduction for MB-OFDM UWB System. - Tai-You Lu; Wei-Zen Chen (ISSCC, 2008)

Low-Power Programmable Pseudorandom Word Generator and Clock Multiplier Unit for High-Speed SerDes Applications. - Wei-Zen Chen; Guan-Sheng Huang (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

A 10-Gbps CMOS single chip optical receiver with 2-D meshed spatially-modulated light detector. - Shih-Hao Huang; Wei-Zen Chen (CICC, 2009)

A 7.1mW 10GHz all-digital frequency synthesizer with dynamically reconfigurable digital loop filter in 90nm CMOS. - Song-Yu Yang; Wei-Zen Chen (ISSCC, 2009)

A Single-Chip 2.5-Gb/s CMOS Burst-Mode Optical Receiver. - Wei-Zen Chen; Ruei-Ming Gan; Shih-Hao Huang (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A 2.4 GHz reference-less wireless receiver for 1Mbps QPSK demodulation. - Wei-Zen Chen; Wei-Wen Ou; Tai-You Lu; Shun-Tien Chou; Song-Yu Yang (ISCAS, 2010)

A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology. - Song-Yu Yang; Wei-Zen Chen; Tai-You Lu (IEEE J. Solid State Circuits, 2010)

Fast analog layout prototyping for nanometer design migration. - Yi-Peng Weng; Hung-Ming Chen; Tung-Chieh Chen; Po-Cheng Pan; Chien-Hung Chen; Wei-Zen Chen (ICCAD, 2011)

A 10-Gb/s OEIC with Meshed Spatially-Modulated Photo Detector in 0.18-μm CMOS Technology. - Shih-Hao Huang; Wei-Zen Chen; Yu-Wei Chang; Yang-Tung Huang (IEEE J. Solid State Circuits, 2011)

A 40 Gbps optical receiver analog front-end in 65 nm CMOS. - Shun-Tien Chou; Shih-Hao Huang; Zheng-Hao Hong; Wei-Zen Chen (ISCAS, 2012)

A 160-GHz receiver-based phase-locked loop in 65 nm CMOS technology. - Wei-Zen Chen; Tai-You Lu; Yan-Ting Wang; Jhong-Ting Jian; Yi-Hung Yang; Guo-Wei Huang; Wen-De Liu; Chih-Hua Hsiao; Shu-Yu Lin; Jung Yen Liao (VLSIC, 2012)

A 2.4 GHz Reference-Less Receiver for 1 Mbps QPSK Demodulation. - Wei-Zen Chen; Tai-You Lu; Wei-Wen Ou; Shun-Tien Chou; Song-Yu Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A 3-10 GHz, 14 Bands CMOS Frequency Synthesizer With Spurs Reduction for MB-OFDM UWB System. - Tai-You Lu; Wei-Zen Chen (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector. - Yao-Chia Liu; Wei-Zen Chen; Mao-Hsuan Chou; Tsung-Hsien Tsai; Yen-Wei Lee; Min-Shueh Yuan (CICC, 2013)

A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression. - Ming-Chiuan Su; Wei-Zen Chen; Pei-Si Wu; Yu-Hsian Chen; Chao-Cheng Lee; Shyh-Jye Jou (CICC, 2013)

A 10Bit, 10MS/s, low power cyclic ADC. - Chien-Hung Chen; Wei-Zen Chen (ICICDT, 2013)

Wide Tunning Range 60 GHz VCO and 40 GHz DCO Using Single Variable Inductor. - Tai-You Lu; Chi-Yao Yu; Wei-Zen Chen; Chung-Yu Wu (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

An 8 Gbps, 4: 1 transition-aware self-toggling multiplexer. - Wei-Zen Chen; Yi-Hung Yang (APCCAS, 2014)

A 3.12 pJ/bit, 19-27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery. - Zheng-Hao Hong; Wei-Zen Chen (A-SSCC, 2014)

A 2 × 20-Gb/s, 1.2-pJ/bit, time-interleaved optical receiver in 40-nm CMOS. - Shih-Hao Huang; Zheng-Hao Hong; Wei-Zen Chen (A-SSCC, 2014)

A 0.6 V, 1.66mW energy harvester and audio driver for tympanic membrane transducer with wirelessly optical signal and power transfer. - Jhong-Ting Jian; Yu-Lin Song; Chia-Fone Lee; Yuan-Fang Chou; Wei-Zen Chen (ISCAS, 2014)

An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programming. - Shih-Hsin Hsu; Wei-Zen Chen; Jui-Pin Zheng; Sean S.-Y. Liu; Po-Cheng Pan; Hung-Ming Chen (VLSI-DAT, 2014)

A 160-GHz Frequency-Translation Phase-Locked Loop With RSSI Assisted Frequency Acquisition. - Wei-Zen Chen; Tai-You Lu; Yan-Ting Wang; Jhong-Ting Jian; Yi-Hung Yang; Kai-Ting Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A 0.4V 53dB SNDR 250 MS/s time-based CT ΔΣ analog to digital converter. - Hung-Kai Chen 001; Wei-Zen Chen; Zhiyuan Ren (ASICON, 2015)

A 25-Gb/s, -10.8-dBm input sensitivity, PD-bandwidth tolerant CMOS optical receiver. - Shih-Hao Huang; Wei-Zen Chen (VLSIC, 2015)

A 3.12 pJ/bit, 19-27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery. - Zheng-Hao Hong; Yao-Chia Liu; Wei-Zen Chen (IEEE J. Solid State Circuits, 2015)

A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression. - Ming-Chiuan Su; Wei-Zen Chen; Pei-Si Wu; Yu-Hsian Chen; Chao-Cheng Lee; Shyh-Jye Jou (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A Low-Jitter Cell-Based Digitally Controlled Oscillator With Differential Multiphase Outputs. - Ming-Chiuan Su; Shyh-Jye Jou; Wei-Zen Chen (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A ΔΣ TDC with sub-ps resolution for PLL built-in phase noise measurement. - Wei-Zen Chen; Po-I Kuo (ESSCIRC, 2016)

Distortion-characteristic estimation predistorter for high efficiency power amplifiers. - Zhiyuan Ren; Hsiao-Hwa Chen; Wei-Zen Chen (IET Signal Process., 2016)

A 25 Gb/s 1.13 pJ/b -10.8 dBm Input Sensitivity Optical Receiver in 40 nm CMOS. - Shih-Hao Huang; Wei-Zen Chen (IEEE J. Solid State Circuits, 2017)

A 40 Gb/s PAM-4 Receiver with 2-Tap DFE Based on Automatically Non-Even Level Tracking. - Chia-Tse Hung; Yu-Ping Huang; Wei-Zen Chen (A-SSCC, 2018)

A 20-Gb/s, 2.4 pJ/bit, Fully Integrated Optical Receiver with a Baud-Rate Clock and Data Recovery. - Yuan-Sheng Lee; Wei-Zen Chen (ISCAS, 2018)

A 25-Gb/s, 2.1-pJ/bit, Fully Integrated Optical Receiver With a Baud-Rate Clock and Data Recovery. - Yuan-Sheng Lee; Wei-Hsiang Ho; Wei-Zen Chen (IEEE J. Solid State Circuits, 2019)

A 50 Gb/s PAM-4 Transmitter with Feedforward Equalizer and Background Phase Error Calibration. - Yu-Ting Lin 010; Wei-Zen Chen (A-SSCC, 2020)

A Millimeter-Wave Frequency Synthesizer for 60 GHz Wireless Interconnect. - Yong-Yu Lin; Fan-ta Chen; Wei-Zen Chen (VLSI-DAT, 2020)

Exploring Multiple Analog Placements With Partial-Monotonic Current Paths and Symmetry Constraints Using PCP-SP. - Abhishek Patyal; Po-Cheng Pan; K. A. Asha; Hung-Ming Chen; Wei-Zen Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A 1.68-23.2 Gb/s Reference-Less Half-Rate Receiver with an ISI-Tolerant Unlimited Range Frequency Detector. - Yu-Ping Huang; Yi-Wei Chang; Wei-Zen Chen (A-SSCC, 2021)

A Single-Channel 1.75GS/s, 6-Bit Flash-Assisted SAR ADC with Self-Adaptive Timer and On-Chip Offset Calibration. - Yu-Sian Liao; Wei-Zen Chen (A-SSCC, 2021)

A 10 GHz Dual-Loop PLL with Active Noise Cancellation Achieving 12dB Spur and 29% Noise Reduction. - Yu-Sian Lu; Cheng-Lung Lee; Wei-Zen Chen (A-SSCC, 2021)

F6: Optical and Electrical Transceivers for 400GbE and Beyond. - Tony Chan Carusone; Sudip Shekhar; Yohan Frans; Wei-Zen Chen; Thomas Toifl; Munehiko Nagatani; Franz Dielacher; William Redman-White (ISSCC, 2021)

Session 11 Overview: Advanced Wireline Links and Techniques Wireline Subcommittee. - Mike Shuo-Wei Chen; Wei-Zen Chen; Amir Amirkhany (ISSCC, 2021)

Introduction to the Special Section on the 2020 Asian Solid-State Circuits Conference (A-SSCC). - Robert Chen-Hao Chang; Wei-Zen Chen; Jun Deguchi (IEEE J. Solid State Circuits, 2021)

A 32 Gb/s PAM-4 Optical Transceiver With Active Back Termination in 40 nm CMOS Technology. - Wei-Hsiang Ho; Yi-Hsun Hsieh; Boris Murmann; Wei-Zen Chen (IEEE Open J. Circuits Syst., 2021)

A 50 Gb/s PAM-4 Transmitter With Feedforward Equalizer and Background Phase Error Calibration. - Yu-Ting Lin 010; Ting-Wei Xu; Wei-Zen Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Reference-Free Phase Noise Measurement Circuit Achieving 24.2-fs Periodic Jitter Sensitivity and 275-fsrms Resolution With Background Self-Calibration. - Wei-Jhih Jian; Wei-Zen Chen (IEEE J. Solid State Circuits, 2023)

A 103 fJ/b/dB, 10-26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement. - Yao-Chia Liu; Wei-Zen Chen; Yuan-Sheng Lee; Yu-Hsiang Chen; Shawn Ming; Ying-Hsi Lin (IEEE J. Solid State Circuits, 2023)

A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction. - Yu-Ping Huang; Yu-Sian Lu; Wei-Zen Chen (IEEE Open J. Circuits Syst., 2024)

Clock and Power Supply-Aware High Accuracy Phase Interpolator Layout Synthesis. - Siou-Sian Lin; Shih-Yu Chen; Yu-Ping Huang; Tzu-Chuan Lin; Hung-Ming Chen; Wei-Zen Chen (DATE, 2025)

Dynamic ADC and Equalizer Adaptation with Background SNR Monitoring for a DSP-Based PAM-4 Receiver. - You-Cheng Tu; Rui-Yong Kuo; Wei-Zen Chen (ISCAS, 2025)

Guest Editorial Introduction to the Special Section on the 2024 IEEE International Solid-State Circuits Conference (ISSCC). - Wei-Zen Chen; Benton H. Calhoun; Chia-Hsiang Yang; Shreyas Sen; Jun Yang (IEEE J. Solid State Circuits, 2025)