Exploiting VLIW schedule slacks for dynamic and leakage energy reduction. - Wei Zhang 002; Narayanan Vijaykrishnan; Mahmut T. Kandemir; Mary Jane Irwin; David Duarte; Yuh-Fang Tsai (MICRO, 2001)

Compiler-directed cache polymorphism. - Jie S. Hu; Mahmut T. Kandemir; Narayanan Vijaykrishnan; Mary Jane Irwin; Hendra Saputra; Wei Zhang 002 (LCTES-SCOPES, 2002)

Compiler-directed instruction cache leakage optimization. - Wei Zhang 002; Jie S. Hu; Vijay Degalahal; Mahmut T. Kandemir; Narayanan Vijaykrishnan; Mary Jane Irwin (MICRO, 2002)

Dynamic Parallelization of Array Based On-Chip Multiprocessor Applications. - Mahmut T. Kandemir; Wei Zhang 002; Mustafa Karaköy (Embedded Software for SoC, 2003)

Data Space Oriented Scheduling. - Mahmut T. Kandemir; Guangyu Chen; Wei Zhang 002; Ibrahim Kolcu (Embedded Software for SoC, 2003)

Energy-Aware Parameter Passing. - Mahmut T. Kandemir; Ibrahim Kolcu; Wei Zhang 002 (Embedded Software for SoC, 2003)

Performance, energy, and reliability tradeoffs in replicating hot cache lines. - Wei Zhang 002; Mahmut T. Kandemir; Anand Sivasubramaniam; Mary Jane Irwin (CASES, 2003)

Interprocedural optimizations for improving data cache performance of array-intensive embedded applications. - Wei Zhang 002; Guangyu Chen; Mahmut T. Kandemir; Mustafa Karaköy (DAC, 2003)

Data Space Oriented Scheduling in Embedded Systems. - Mahmut T. Kandemir; Guangyu Chen; Wei Zhang 002; Ibrahim Kolcu (DATE, 2003)

Implementation and Evaluation of an On-Demand Parameter-Passing Strategy for Reducing Energy. - Mahmut T. Kandemir; Ibrahim Kolcu; Wei Zhang 002 (DATE, 2003)

Runtime Code Parallelization for On-Chip Multiprocessors. - Mahmut T. Kandemir; Wei Zhang 002; Mustafa Karaköy (DATE, 2003)

Masking the Energy Behavior of DES Encryption. - Hendra Saputra; Narayanan Vijaykrishnan; Mahmut T. Kandemir; Mary Jane Irwin; Richard R. Brooks; Soontae Kim; Wei Zhang 002 (DATE, 2003)

Compiler Support for Reducing Leakage Energy Consumption. - Wei Zhang 002; Mahmut T. Kandemir; Narayanan Vijaykrishnan; Mary Jane Irwin; Vivek De (DATE, 2003)

Compiler-Directed Management of Instruction Accesses. - Guilin Chen; Guangyu Chen; Ismail Kadayif; Wei Zhang 002; Mahmut T. Kandemir; Ibrahim Kolcu; Ugur Sezer (DSD, 2003)

ICR: In-Cache Replication for Enhancing Data Cache Reliability. - Wei Zhang 002; Sudhanva Gurumurthi; Mahmut T. Kandemir; Anand Sivasubramaniam (DSN, 2003)

A compiler approach for reducing data cache energy. - Wei Zhang 002; Mustafa Karaköy; Mahmut T. Kandemir; Guangyu Chen (ICS, 2003)

Replica Victim Caching to Improve Reliability of In-Cache Replication. - Wei Zhang 002 (Asia-Pacific Computer Systems Architecture Conference, 2004)

Static next sub-bank prediction for drowsy instruction cache. - Bramha Allu; Wei Zhang 002 (CASES, 2004)

Loop-based leakage control for branch predictors. - Wei Zhang 002; Bramha Allu (CASES, 2004)

Enhancing data cache reliability by the addition of a small fully-associative replication cache. - Wei Zhang 002 (ICS, 2004)

Compiler-Directed Data Cache Leakage Reduction. - Wei Zhang 002 (ISVLSI, 2004)

Reducing instruction cache energy consumption using a compiler-based strategy. - Wei Zhang 002; Jie S. Hu; Vijay Degalahal; Mahmut T. Kandemir; Narayanan Vijaykrishnan; Mary Jane Irwin (ACM Trans. Archit. Code Optim., 2004)

Object Class Recognition Using Multiple Layer Boosting with Heterogeneous Features. - Wei Zhang 002; Bing Yu; Gregory J. Zelinsky; Dimitris Samaras (CVPR (2), 2005)

Computing Cache Vulnerability to Transient Errors and Its Implication. - Wei Zhang 002 (DFT, 2005)

Compiler-guided register reliability improvement against soft errors. - Jun Yan 008; Wei Zhang 002 (EMSOFT, 2005)

The Role of Top-down and Bottom-up Processes in Guiding Eye Movements during Visual Search. - Gregory J. Zelinsky; Wei Zhang 002; Bing Yu; Xin Chen; Dimitris Samaras (NIPS, 2005)

A Computational Model of Eye Movements during Object Class Detection. - Wei Zhang 002; Hyejin Yang; Dimitris Samaras; Gregory J. Zelinsky (NIPS, 2005)

Exploiting loop behavior for data cache leakage reduction. - Wei Zhang 002 (J. Embed. Comput., 2005)

Exploiting the replication cache to improve performance for multiple-issue microprocessors. - Bramha Allu; Wei Zhang 002 (SIGARCH Comput. Archit. News, 2005)

Replication Cache: A Small Fully Associative Cache to Improve Data Cache Reliability. - Wei Zhang 002 (IEEE Trans. Computers, 2005)

Reducing data cache leakage energy using a compiler-based approach. - Wei Zhang 002; Mahmut T. Kandemir; Mustafa Karaköy; Guangyu Chen (ACM Trans. Embed. Comput. Syst., 2005)

The Impact of Cache Organization in Optimizing Microprocessor Power Consumption. - Nagm Mohamed; Nazeih Botros; Wei Zhang 002 (CDES, 2006)

Compiler-guided next sub-bank prediction for reducing instruction cache leakage energy. - Wei Zhang 002 (J. Embed. Comput., 2006)

Reducing Instruction Translation Look-Aside Buffer Energy Through Compiler-Directed Resizing. - Bramha Allu; Wei Zhang 002 (J. Low Power Electron., 2006)

Reducing dynamic and leakage energy in VLIW architectures. - Wei Zhang 002; Yuh-Fang Tsai; David Duarte; Narayanan Vijaykrishnan; Mahmut T. Kandemir; Mary Jane Irwin (ACM Trans. Embed. Comput. Syst., 2006)

An Area-Efficient Approach to Improving Register File Reliability against Transient Errors. - Mallik Kandala; Wei Zhang 002; Laurence Tianruo Yang (AINA Workshops (1), 2007)

Detecting VLIW Hard Errors Cost-Effectively through a Software-Based Approach. - Abhishek Pillai; Wei Zhang 002; Dimitrios Kagaris (AINA Workshops (1), 2007)

Exploring Functional Unit Design Space of VLIW Processors for Optimizing Both Performance and Energy Consumption. - Abhishek Pillai; Wei Zhang 002; Laurence Tianruo Yang (AINA Workshops (1), 2007)

Virtual Registers: Reducing Register Pressure Without Enlarging the Register File. - Jun Yan 008; Wei Zhang 002 (HiPEAC, 2007)

Real-time Accurate Object Detection using Multiple Resolutions. - Wei Zhang 002; Gregory J. Zelinsky; Dimitris Samaras (ICCV, 2007)

WCET analysis of instruction caches with prefetching. - Jun Yan 008; Wei Zhang 002 (LCTES, 2007)

Compiler-Assisted Leakage Energy Reduction for Cache Memories. - Wei Zhang 002 (Adv. Comput., 2007)

Hybrid multi-core architecture for boosting single-threaded performance. - Jun Yan 008; Wei Zhang 002 (SIGARCH Comput. Archit. News, 2007)

Evaluating instruction cache vulnerability to transient errors. - Jun Yan 008; Wei Zhang 002 (SIGARCH Comput. Archit. News, 2007)

Reducing branch predictor leakage energy by exploiting loops. - Wei Zhang 002; Bramha Allu (ACM Trans. Embed. Comput. Syst., 2007)

Efficient code caching to improve performance and energy consumption for java applications. - Yu Sun 006; Wei Zhang 002 (CASES, 2008)

On the Energy Efficiency of Java Virtual Machine. - Yu Sun 006; Wei Zhang 002 (ESA, 2008)

Adaptive Drowsy Cache Control for Java Applications. - Yu Sun 006; Wei Zhang 002 (EUC (1), 2008)

Improving code caching performance for Java applications. - Yu Sun 006; Wei Zhang 002 (IPDPS, 2008)

WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches. - Jun Yan 008; Wei Zhang 002 (IEEE Real-Time and Embedded Technology and Applications Symposium, 2008)

A time-predictable VLIW processor and its compiler support. - Jun Yan 008; Wei Zhang 002 (Real Time Syst., 2008)

Exploiting virtual registers to reduce pressure on real registers. - Jun Yan 008; Wei Zhang 002 (ACM Trans. Archit. Code Optim., 2008)

Analyzing the worst-case execution time for instruction caches with prefetching. - Jun Yan 008; Wei Zhang 002 (ACM Trans. Embed. Comput. Syst., 2008)

Exploiting Multi-core Processors to Improve Time Predictability for Real-Time Java Computing. - Yu Sun 006; Wei Zhang 002 (RTCSA, 2009)

Accurately Estimating Worst-Case Execution Time for Multi-core Processors with Shared Direct-Mapped Instruction Caches. - Wei Zhang 002; Jun Yan 008 (RTCSA, 2009)

Exploiting stack distance to estimate worst-case data cache performance. - Yu Liu 037; Wei Zhang 002 (SAC, 2009)

Improving Java performance and energy dissipation through efficient code caching. - Yu Sun 006; Wei Zhang 002 (Des. Autom. Embed. Syst., 2009)

Computing and Minimizing Cache Vulnerability to Transient Errors. - Wei Zhang 002 (IEEE Des. Test Comput., 2009)

Studying Energy-Oriented Dynamic Optimizations in Java Virtual Machines. - Yu Sun 006; Wei Zhang 002 (J. Circuits Syst. Comput., 2009)

Boosting the Performance of Software-Based Transient Errors Tolerant Techniques through Compiler Optimizations. - Wei Zhang 002 (J. Circuits Syst. Comput., 2009)

Optimizing Instruction Prefetching to Improve Worst-Case Performance for Real-Time Applications. - Yiqiang Ding; Jun Yan 008; Wei Zhang 002 (J. Comput. Sci. Eng., 2009)

Bounding Worst-Case Data Cache Performance by Using Stack Distance. - Yu Liu 037; Wei Zhang 002 (J. Comput. Sci. Eng., 2009)

Improving the static real-time scheduling on multicore processors by reducing worst-case inter-thread cache interferences. - Yiqiang Ding; Wei Zhang 002 (ACM Southeast Regional Conference, 2010)

A time-predictable dual-core prototype on FPGA. - Satya Mohan Raju Gudidevuni; Wei Zhang 002 (ACM Southeast Regional Conference, 2010)

Time-Predictable L2 Cache Design for High-Performance Real-Time Systems. - Jun Yan 008; Wei Zhang 002 (RTCSA, 2010)

Design and implementation of hybrid multicore simulators. - Jun Yan 008; Wei Zhang 002 (Int. J. Embed. Syst., 2010)

Replica victim caching to improve cache reliability against transient errors. - Wei Zhang 002 (Int. J. High Perform. Syst. Archit., 2010)

Time-dependent density functional theory study on the hydrogen bonding-induced twisted intramolecular charge-transfer excited states of 2-(4'-N, N-dimethylaminophenyl)imidazo[4, 5-b]pyridine. - Shu-Hui Yin; Yufang Liu; Wei Zhang 002; Ming-Xing Guo; Peng Song 021 (J. Comput. Chem., 2010)

Static Worst-Case Energy and Lifetime Estimation of Wireless Sensor Networks. - Yu Liu 037; Wei Zhang 002; Kemal Akkaya (J. Comput. Sci. Eng., 2010)

Loop-Based Instruction Prefetching to Reduce the Worst-Case Execution Time. - Yiqiang Ding; Wei Zhang 002 (IEEE Trans. Computers, 2010)

Work in progress - Course development of programming for general-purpose multicore processors. - Wei Zhang 002 (FIE, 2011)

Static Worst-Case Lifetime Estimation of Vigil Net. - Yu Liu 037; Wei Zhang 002 (GreenCom, 2011)

Multicore-Aware Code Positioning to Improve Worst-Case Performance. - Yiqiang Ding; Wei Zhang 002 (ISORC, 2011)

Exploiting time predictable two-level scratchpad memory for real-time systems. - Yu Liu 037; Wei Zhang 002 (SAC, 2011)

Stack distance based worst-case instruction cache performance analysis. - Yu Liu 037; Wei Zhang 002 (SAC, 2011)

Exploiting Instruction Reuse to Improve the Performance of Dual Instruction Execution. - Abhishek Pillai; Wei Zhang 002 (J. Circuits Syst. Comput., 2011)

Bounding Worst-Case Performance for Multi-Core Processors with Shared L2 Instruction Caches. - Jun Yan 008; Wei Zhang 002 (J. Comput. Sci. Eng., 2011)

Computing and Reducing Transient Error Propagation in Registers. - Jun Yan 008; Wei Zhang 002 (J. Comput. Sci. Eng., 2011)

An Interference Matrix Based Approach to Bounding Worst-Case Inter-Thread Cache Interferences and WCET for Multi-Core Processors. - Jun Yan 008; Wei Zhang 002 (J. Comput. Sci. Eng., 2011)

Exploiting SPM-aware Scheduling on EPIC architectures for high-performance real-time systems. - Yu Liu 037; Wei Zhang 002 (HPEC, 2012)

Exploiting multi-level scratchpad memories for time-predictable multicore computing. - Yu Liu 037; Wei Zhang 002 (ICCD, 2012)

Static Timing Analysis of Shared Caches for Multicore Processors. - Wei Zhang 002; Jun Yan 008 (J. Comput. Sci. Eng., 2012)

Multicore-Aware Code Co-Positioning to Reduce WCET on Dual-Core Processors with Shared Instruction Caches. - Yiqiang Ding; Wei Zhang 002 (J. Comput. Sci. Eng., 2012)

Time-Predictable Java Dynamic Compilation on Multicore Processors. - Yu Sun 006; Wei Zhang 002 (J. Comput. Sci. Eng., 2012)

On-line Trace Based Automatic Parallelization of Java Programs on Multicore Platforms. - Yu Sun 006; Wei Zhang 002 (J. Comput. Sci. Eng., 2012)

Architectural time-predictability factor (ATF): a metric to evaluate time predictability of processors. - Yiqiang Ding; Wei Zhang 002 (SIGBED Rev., 2012)

A Model Checking Based Approach to Bounding Worst-Case Execution Time for Multicore Processors. - Lan Wu; Wei Zhang 002 (ACM Trans. Embed. Comput. Syst., 2012)

Standard deviation of CPI: A new metric to evaluate architectural time predictability. - Wei Zhang 002; Yiqiang Ding (ASAP, 2013)

Hybrid SPM-cache architectures to achieve high time predictability and performance. - Wei Zhang 002; Yiqiang Ding (ASAP, 2013)

Compiler-based approach to reducing leakage energy of instruction scratch-pad memories. - Yijie Huangfu; Wei Zhang 002 (ICCD, 2013)

Reducing worst-case execution time of hybrid SPM-caches. - Lan Wu; Wei Zhang 002 (IPCCC, 2013)

Defend GPUs against DoS attacks. - Wei Zhang 002 (IPCCC, 2013)

On the interactions between real-time scheduling and inter-thread cached interferences for multicore processors. - Yiqiang Ding; Wei Zhang 002 (ISQED, 2013)

Multicore Real-Time Scheduling to Reduce Inter-Thread Cache Interferences. - Yiqiang Ding; Wei Zhang 002 (J. Comput. Sci. Eng., 2013)

Counter-Based Approaches for Efficient WCET Analysis of Multicore Processors with Shared Caches. - Yiqiang Ding; Wei Zhang 002 (J. Comput. Sci. Eng., 2013)

Bounding Worst-Case DRAM Performance on Multicore Processors. - Yiqiang Ding; Lan Wu; Wei Zhang 002 (J. Comput. Sci. Eng., 2013)

Overview of Real-Time Java Computing. - Yu Sun 006; Wei Zhang 002 (J. Comput. Sci. Eng., 2013)

Static worst-case lifetime estimation of wireless sensor networks: A case study on VigilNet. - Yu Liu 037; Wei Zhang 002 (J. Syst. Archit., 2013)

Reducing cache leakage energy for hybrid SPM-cache architectures. - Hao Wen 002; Wei Zhang 002 (CASES, 2014)

Hop-Based Priority Scheduling to Improve Worst-Case Inter-core Communication Latency. - Yiqiang Ding; Wei Zhang 002 (EUC, 2014)

Improving Energy Efficiency with Dynamic Compiler-Directed Function Unit Power Control. - Yu Sun 006; Wei Zhang 002 (EUC, 2014)

Bounding the Worst-Case Execution Time of Static NUCA Caches. - Yiqiang Ding; Wei Zhang 002 (HPCC/CSS/ICESS, 2014)

Performance Implication of Multicore Cache Locking on General-Purpose Processors. - Matthew Loach; Wei Zhang 002 (HPCC/CSS/ICESS, 2014)

Characterizing Energy Consumption of Real-Time and Media Benchmarks on Hybrid SPM-Caches. - Lan Wu; Yiqiang Ding; Wei Zhang 002 (HPCC/CSS/ICESS, 2014)

Exploiting Hybrid SPM-Cache Architectures to Reduce Energy Consumption for Embedded Computing. - Wei Zhang 002; Lan Wu (HPCC/CSS/ICESS, 2014)

WCET analysis of static NUCA caches. - Yiqiang Ding; Wei Zhang 002 (IPCCC, 2014)

Worst-case performance guaranteed data cache. - Yijie Huangfu; Wei Zhang 002 (IPCCC, 2014)

A Real-Time Instruction Cache with High Average-Case Performance. - Yijie Huangfu; Wei Zhang 002 (ISORC, 2014)

Compiler-directed leakage energy reduction for instruction scratch-pad memories. - Yijie Huangfu; Wei Zhang 002 (ISQED, 2014)

PEG-C: Performance Enhancement Guaranteed Cache for Hard Real-Time Systems. - Yijie Huangfu; Wei Zhang 002 (IEEE Embed. Syst. Lett., 2014)

Two-Level Scratchpad Memory Architectures to Achieve Time Predictability and High Performance. - Yu Liu 037; Wei Zhang 002 (J. Comput. Sci. Eng., 2014)

Comparing Separate and Statically-Partitioned Caches for Time-Predictable Multicore Processors. - Lan Wu; Yiqiang Ding; Wei Zhang 002 (J. Comput. Sci. Eng., 2014)

Exploiting Standard Deviation of CPI to Evaluate Architectural Time-Predictability. - Wei Zhang 002; Yiqiang Ding (J. Comput. Sci. Eng., 2014)

Boosting GPU Performance by Profiling-Based L1 Data Cache Bypassing. - Yijie Huangfu; Wei Zhang 002 (CCGRID, 2015)

Hardware-Based and Hybrid L1 Data Cache Bypassing to Improve GPU Performance. - Yijie Huangfu; Wei Zhang 002 (HPCC/CSS/ICESS, 2015)

Hardware-Based Performance Enhancement Guaranteed Caches. - Yijie Huangfu; Wei Zhang 002 (ISORC, 2015)

Real-Time GPU Computing: Cache or No Cache? - Yijie Huangfu; Wei Zhang 002 (ISORC, 2015)

Exploring shared memory and cache to improve GPU performance and energy efficiency. - Hao Wen 002; Wei Zhang 002 (ISQED, 2015)

Cache-aware SPM allocation algorithms for hybrid SPM-cache architectures. - Lan Wu; Wei Zhang 002 (ISQED, 2015)

Exploiting Static Non-Uniform Cache Architectures for Hard Real-Time Computing. - Yiqiang Ding; Wei Zhang 002 (J. Comput. Sci. Eng., 2015)

Scratchpad Memory Architectures and Allocation Algorithms for Hard Real-Time Multicore Processors. - Yu Liu 037; Wei Zhang 002 (J. Comput. Sci. Eng., 2015)

Profiling-based L1 data cache bypassing to improve GPU performance and energy efficiency. - Yijie Huangfu; Wei Zhang 002 (SIGBED Rev., 2015)

Cache locking vs. partitioning for real-time computing on integrated CPU-GPU processors. - Xin Wang 056; Wei Zhang 002 (IPCCC, 2016)

Warp-Based Load/Store Reordering to Improve GPU Data Cache Time Predictability and Performance. - Yijie Huangfu; Wei Zhang 002 (ISORC, 2016)

Priority L2 cache design for time predictability. - Jun Yan 008; Wei Zhang 002 (Int. J. Embed. Syst., 2016)

WCET analysis of the shared data cache in integrated CPU-GPU architectures. - Yijie Huangfu; Wei Zhang 002 (HPEC, 2017)

Leakage energy reduction for hard real-time caches. - Yijie Huangfu; Wei Zhang 002 (HPEC, 2017)

Drowsy Register Files for Reducing GPU Leakage Energy. - Xin Wang 056; Wei Zhang 002 (ICPADS, 2017)

Static WCET Analysis of GPUs with Predictable Warp Scheduling. - Yijie Huangfu; Wei Zhang 002 (ISORC, 2017)

GPU Register Packing: Dynamically Exploiting Narrow-Width Operands to Improve Performance. - Xin Wang 056; Wei Zhang 002 (TrustCom/BigDataSE/ICESS, 2017)

A Sample-Based Dynamic CPU and GPU LLC Bypassing Method for Heterogeneous CPU-GPU Architectures. - Xin Wang 056; Wei Zhang 002 (TrustCom/BigDataSE/ICESS, 2017)

Warp-Based Load/Store Reordering to Improve GPU Time Predictability. - Yijie Huangfu; Wei Zhang 002 (J. Comput. Sci. Eng., 2017)

Enhancing GPU Performance by Efficient Hardware-Based and Hybrid L1 Data Cache Bypassing. - Yijie Huangfu; Wei Zhang 002 (J. Comput. Sci. Eng., 2017)

WCET Analysis of GPU L1 Data Caches. - Yijie Huangfu; Wei Zhang 002 (HPEC, 2018)

Energy-Efficient DNN Computing on GPUs Through Register File Management. - Xin Wang 056; Wei Zhang 002 (HPEC, 2018)

Regression Based WCET Analysis For Sampling Based Motion Planning. - Hao Wen 002; Wei Zhang 002 (HPEC, 2018)

Exploiting GPU with 3D Stacked Memory to Boost Performance for Data-Intensive Applications. - Hao Wen 002; Wei Zhang 002 (HPEC, 2018)

Reducing Inter-Application Interferences in Integrated CPU-GPU Heterogeneous Architecture. - Hao Wen 002; Wei Zhang 002 (ICCD, 2018)

Cache-Aware SPM Allocation to Reduce Worst-Case Execution Time for Hybrid SPM-Caches. - Lan Wu; Wei Zhang 002 (J. Circuits Syst. Comput., 2018)

Packing Narrow-Width Operands to Improve GPU Performance. - Xin Wang 056; Wei Zhang 002 (J. Comput. Sci. Eng., 2018)

Improving CPU and GPU Performance through Sample-Based Dynamic LLC Bypassing. - Xin Wang 056; Wei Zhang 002 (J. Comput. Sci. Eng., 2018)

Estimating the Worst-Case Execution Time of the Shared Data Cache in Integrated CPU-GPU Architectures. - Yijie Huangfu; Wei Zhang 002 (J. Comput. Sci. Eng., 2018)

Exploring GPU Data Cache Leakage Management Techniques. - Hao Wen 002; Wei Zhang 002 (J. Comput. Sci. Eng., 2018)

Cache-Aware SPM Allocation Algorithms for Performance and Energy Optimization on Hybrid SPM-Cache Architecture. - Lan Wu; Wei Zhang 002 (J. Comput. Sci. Eng., 2018)

Heterogeneous Cache Hierarchy Management for Integrated CPU-GPU Architecture. - Hao Wen 002; Wei Zhang 002 (HPEC, 2019)

Improving Parallelism of Breadth First Search (BFS) Algorithm for Accelerated Performance on GPUs. - Hao Wen 002; Wei Zhang 002 (HPEC, 2019)

Cracking Randomized Coalescing Techniques with An Efficient Profiling-Based Side-Channel Attack to GPU. - Xin Wang 056; Wei Zhang 002 (HASP@ISCA, 2019)

A Collaborative Neurodynamic Approach to Sparse Coding. - Hangjun Che; Jun Wang 002; Wei Zhang 002 (ISNN (1), 2019)

Execution Units Power-Gating to Improve Energy Efficiency of GPGPUs. - Xin Wang 056; Wei Zhang 002 (iThings/GreenCom/CPSCom/SmartData, 2019)

An Efficient Profiling-Based Side-Channel Attack on Graphics Processing Units. - Xin Wang 056; Wei Zhang 002 (NCS, 2019)

Packing Narrow-Width Operands to Improve Energy Efficiency of General-Purpose GPU Computing. - Xin Wang 056; Wei Zhang 002 (HPEC, 2020)

Denial of Service in CPU-GPU Heterogeneous Architectures. - Hao Wen 002; Wei Zhang 002 (HPEC, 2020)

pacSCA: A Profiling-Assisted Correlation-based Side-Channel Attack on GPUs. - Xin Wang 056; Wei Zhang 002 (ICCD, 2020)

Reducing CPU-GPU Interferences to Improve CPU Performance in Heterogeneous Architectures. - Hao Wen 002; Wei Zhang 002 (J. Comput. Sci. Eng., 2020)

Cache Leakage Reduction Techniques for Hybrid SPM-Cache Architectures. - Hao Wen 002; Wei Zhang 002 (J. Circuits Syst. Comput., 2021)