ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology. - Wei Zhang 012; Niraj K. Jha (ICCD, 2005)

NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture. - Wei Zhang 012; Niraj K. Jha; Li Shang (DAC, 2006)

NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture. - Wei Zhang 012; Li Shang; Niraj K. Jha (DAC, 2007)

A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip. - Huaxi Gu; Jiang Xu 001; Wei Zhang 012 (DATE, 2009)

A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip. - Huaxi Gu; Mo Kwai Hung Morton; Jiang Xu 001; Wei Zhang 012 (ISVLSI, 2009)

A hybrid Nano/CMOS dynamically reconfigurable system - Part II: Design optimization flow. - Wei Zhang 012; Niraj K. Jha; Li Shang (ACM J. Emerg. Technol. Comput. Syst., 2009)

A hybrid nano/CMOS dynamically reconfigurable system - Part I: Architecture. - Wei Zhang 012; Niraj K. Jha; Li Shang (ACM J. Emerg. Technol. Comput. Syst., 2009)

Design space exploration and data memory architecture design for a hybrid nano/CMOS dynamically reconfigurable architecture. - Wei Zhang 012; Niraj K. Jha; Li Shang (ACM J. Emerg. Technol. Comput. Syst., 2009)

Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs. - Jiang Xu 001; Wayne H. Wolf; Wei Zhang 012 (IEEE Micro, 2009)

Crosstalk noise and bit error rate analysis for optical network-on-chip. - Yiyuan Xie; Mahdi Nikdast; Jiang Xu 001; Wei Zhang 012; Qi Li 013; Xiaowen Wu; Yaoyao Ye; Xuan Wang 001; Weichen Liu (DAC, 2010)

A Hierarchical Hybrid Optical-Electronic Network-on-Chip. - Mo Kwai Hung; Yaoyao Ye; Xiaowen Wu; Wei Zhang 012; Weichen Liu; Jiang Xu 001 (ISVLSI, 2010)

UNION: A unified inter/intra-chip optical network for chip multiprocessors. - Xiaowen Wu; Yaoyao Ye; Wei Zhang 012; Weichen Liu; Mahdi Nikdast; Xuan Wang 001; Jiang Xu 001 (NANOARCH, 2010)

Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture. - Wei Zhang 012; Niraj K. Jha; Li Shang (ACM J. Emerg. Technol. Comput. Syst., 2010)

Power Dissipation. - Wei Zhang 012; James Williamson; Li Shang (Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011)

Case study: Alleviating hotspots and improving chip reliability via carbon nanotube thermal interface. - Wei Zhang 012; Jiale Huang; Shengqi Yang; Pallav Gupta (DATE, 2011)

A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC. - Weichen Liu; Jiang Xu 001; Xuan Wang 001; Yu Wang 002; Wei Zhang 012; Yaoyao Ye; Xiaowen Wu; Mahdi Nikdast; Zhehui Wang (ISVLSI, 2011)

A NoC Traffic Suite Based on Real Applications. - Weichen Liu; Jiang Xu 001; Xiaowen Wu; Yaoyao Ye; Xuan Wang 001; Wei Zhang 012; Mahdi Nikdast; Zhehui Wang (ISVLSI, 2011)

Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip. - Yaoyao Ye; Jiang Xu 001; Xiaowen Wu; Wei Zhang 012; Xuan Wang 001; Mahdi Nikdast; Zhehui Wang; Weichen Liu (ISVLSI, 2011)

3D-HIM: A 3D High-density Interleaved Memory for bipolar RRAM design. - Yi-Chung Chen; Hai Li 001; Wei Zhang 012; Robinson E. Pino (NANOARCH, 2011)

NEMS based thermal management for 3D many-core system. - Xiwei Huang; Hao Yu 001; Wei Zhang 012 (NANOARCH, 2011)

Coroutine-Based Synthesis of Efficient Embedded Software From SystemC Models. - Weichen Liu; Jiang Xu 001; Jogesh K. Muppala; Wei Zhang 012; Xiaowen Wu; Yaoyao Ye (IEEE Embed. Syst. Lett., 2011)

Fine-grained dynamic voltage scaling on OLED display. - Xiang Chen 010; Jian Zheng; Yiran Chen 001; Wei Zhang 012; Hai Li 001 (ASP-DAC, 2012)

A Look Up Table design with 3D bipolar RRAMs. - Yi-Chung Chen; Wei Zhang 012; Hai Li 001 (ASP-DAC, 2012)

Non-volatile 3D stacking RRAM-based FPGA. - Yi-Chung Chen; Wenhua Wang; Hai Li 001; Wei Zhang 012 (FPL, 2012)

uBRAM-based run-time reconfigurable FPGA and corresponding reconfiguration methodology. - Yi-Chung Chen; Wenhua Wang; Wei Zhang 012; Hai Li 001 (FPT, 2012)

A thermal and process variation aware MTJ switching model and its applications in soft error analysis. - Peiyuan Wang; Wei Zhang 012; Rajiv V. Joshi; Rouwaida Kanj; Yiran Chen 001 (ICCAD, 2012)

Distributed thermal-aware task scheduling for 3D Network-on-Chip. - Yingnan Cui; Wei Zhang 012; Hao Yu 001 (ICCD, 2012)

A novel peripheral circuit for RRAM-based LUT. - Yi-Chung Chen; Hai Li 001; Wei Zhang 012 (ISCAS, 2012)

Decentralized agent based re-clustering for task mapping of tera-scale network-on-chip system. - Yingnan Cui; Wei Zhang 012; Hao Yu 001 (ISCAS, 2012)

Design of low power 3D hybrid memory by non-volatile CBRAM-crossbar with block-level data-retention. - Yuhao Wang 002; Chun Zhang; Hao Yu 001; Wei Zhang 012 (ISLPED, 2012)

A physical design tool for carbon nanotube field-effect transistor circuits. - Jiale Huang; Minhao Zhu; Shengqi Yang; Pallav Gupta; Wei Zhang 012; Steven M. Rubin; Gilda Garretón; Jin He 003 (ACM J. Emerg. Technol. Comput. Syst., 2012)

A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip. - Yaoyao Ye; Jiang Xu 001; Xiaowen Wu; Wei Zhang 012; Weichen Liu; Mahdi Nikdast (ACM J. Emerg. Technol. Comput. Syst., 2012)

Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis. - Wei Fei; Hao Yu 001; Wei Zhang 012; Kiat Seng Yeo (IEEE Trans. Very Large Scale Integr. Syst., 2012)

SRAM-Based NATURE: A Dynamically Reconfigurable FPGA Based on 10T Low-Power SRAMs. - Ting-Jung Lin; Wei Zhang 012; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effects. - Hanhua Qian; Hao Liang 003; Chip-Hong Chang; Wei Zhang 012; Hao Yu 001 (ASP-DAC, 2013)

Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine. - Beiye Liu; Miao Hu 002; Hai Li 001; Zhi-Hong Mao; Yiran Chen 001; Tingwen Huang; Wei Zhang 012 (DAC, 2013)

Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories. - Xuan Wang 001; Jiang Xu 001; Wei Zhang 012; Xiaowen Wu; Yaoyao Ye; Zhehui Wang; Mahdi Nikdast; Zhe Wang 003 (DATE, 2013)

A hardware security scheme for RRAM-based FPGA. - Yi-Chung Chen; Wei Zhang 012; Hai (Helen) Li (FPL, 2013)

NBTI-aware circuit node criticality computation. - Shengqi Yang; Wenping Wang 004; Mark Hagan; Wei Zhang 012; Pallav Gupta; Yu Cao 001 (ACM J. Emerg. Technol. Comput. Syst., 2013)

3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip. - Yaoyao Ye; Jiang Xu 001; Baihan Huang; Xiaowen Wu; Wei Zhang 012; Xuan Wang 001; Mahdi Nikdast; Zhehui Wang; Weichen Liu; Zhe Wang 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

A New RNS based DA Approach for Inner Product Computation. - Chan Hua Vun; A. Benjamin Premkumar; Wei Zhang 012 (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip. - Yiyuan Xie; Mahdi Nikdast; Jiang Xu 001; Xiaowen Wu; Wei Zhang 012; Yaoyao Ye; Xuan Wang 001; Zhehui Wang; Weichen Liu (IEEE Trans. Very Large Scale Integr. Syst., 2013)

System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip. - Yaoyao Ye; Jiang Xu 001; Xiaowen Wu; Wei Zhang 012; Xuan Wang 001; Mahdi Nikdast; Zhehui Wang; Weichen Liu (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Soft error mitigation through selection of noninvert implication paths. - Bin Zhou; Thambipillai Srikanthan; Wei Zhang 012 (AHS, 2014)

An extended framework for worst-case throughput analysis with router constraint. - Vineeth Mohan; Wenjing Hsu; Wei Zhang 012; Xiaowen Wu (APCCAS, 2014)

A low cost acceleration method for hardware trojan detection based on fan-out cone analysis. - Bin Zhou; Wei Zhang 012; Thambipillai Srikanthan; J. K. J. Teo (CODES+ISSS, 2014)

Hierarchical library-based power estimator for versatile FPGAs (abstract only). - Hao Liang 003; Yi-Chung Chen; Wei Zhang 012; Hai Li 001 (FPGA, 2014)

BMP: a fast B*-tree based modular placer for FPGAs (abstract only). - Fubing Mao; Yi-Chung Chen; Wei Zhang 012; Hai Li 001 (FPGA, 2014)

Towards automatic partial reconfiguration in FPGAs. - Fubing Mao; Wei Zhang 012; Bingsheng He (FPT, 2014)

A low-power pipelined MAC architecture using Baugh-Wooley based multiplier. - Rakesh Warrier; Chan Hua Vun; Wei Zhang 012 (GCCE, 2014)

Reconfigurable DSP block design for dynamically reconfigurable architecture. - Rakesh Warrier; Hao Liang 003; Wei Zhang 012 (ISCAS, 2014)

Sum of products: Computation using modular thermometer codes. - Chan Hua Vun; A. Benjamin Premkumar; Wei Zhang 012 (ISPACS, 2014)

Reconfigurable Dynamic Trusted Platform Module for Control Flow Checking. - Sanjeev Das; Wei Zhang 012; Yang Liu 003 (ISVLSI, 2014)

Thermal-aware task scheduling for peak temperature minimization under periodic constraint for 3D-MPSoCs. - Vivek Chaturvedi; Amit Kumar Singh 002; Wei Zhang 012; Thambipillai Srikanthan (RSP, 2014)

On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip. - Weichen Liu; Xuan Wang 001; Jiang Xu 001; Wei Zhang 012; Yaoyao Ye; Xiaowen Wu; Mahdi Nikdast; Zhehui Wang (ACM J. Emerg. Technol. Comput. Syst., 2014)

Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors. - Zhehui Wang; Jiang Xu 001; Xiaowen Wu; Yaoyao Ye; Wei Zhang 012; Mahdi Nikdast; Xuan Wang 001; Zhe Wang 003 (IEEE Trans. Computers, 2014)

Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip. - Mahdi Nikdast; Jiang Xu 001; Xiaowen Wu; Wei Zhang 012; Yaoyao Ye; Xuan Wang 001; Zhehui Wang; Zhe Wang 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

A Fine-Grain Dynamically Reconfigurable Architecture Aimed at Reducing the FPGA-ASIC Gaps. - Ting-Jung Lin; Wei Zhang 012; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Nonvolatile CBRAM-Crossbar-Based 3-D-Integrated Hybrid Memory for Data Retention. - Yuhao Wang 002; Hao Yu 001; Wei Zhang 012 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors. - Xiaowen Wu; Yaoyao Ye; Jiang Xu 001; Wei Zhang 012; Weichen Liu; Mahdi Nikdast; Xuan Wang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Motion Compensation Based Fast Moving Object Detection in Dynamic Background. - Wei Zhang 012; Chenglong Li 002; Aihua Zheng; Jin Tang 001; Bin Luo 001 (CCCV (2), 2015)

Improving Data Partitioning Performance on OpenCL-Based FPGAs. - Ze-ke Wang; Bingsheng He; Wei Zhang 012 (FCCM, 2015)

Static hardware task placement on multi-context FPGA using hybrid genetic algorithm. - Hao Liang 003; Sharad Sinha; Rakesh Warrier; Wei Zhang 012 (FPL, 2015)

Hierarchical library based power estimator for versatile FPGAs. - Hao Liang 003; Wei Zhang 012; Sharad Sinha; Yi-Chung Chen; Hai Li 001 (FPL, 2015)

A study of data partitioning on OpenCL-based FPGAs. - Ze-ke Wang; Bingsheng He; Wei Zhang 012 (FPL, 2015)

An Efficient Technique for Chip Temperature Optimization of Multiprocessor Systems in the Dark Silicon Era. - Mengquan Li; Juan Yi; Weichen Liu; Wei Zhang 012; Lei Yang 018; Edwin Hsing-Mean Sha (HPCC/CSS/ICESS, 2015)

Traffic-Aware Application Mapping for Network-on-Chip Based Multiprocessor System-on-Chip. - Lei Yang 018; Weichen Liu; Weiwen Jiang; Wei Zhang 012; Mengquan Li; Juan Yi; Duo Liu; Edwin Hsing-Mean Sha (HPCC/CSS/ICESS, 2015)

Hierarchical Library Based Power Estimator for Versatile FPGAs. - Hao Liang 003; Yi-Chung Chen; Tao Luo 014; Wei Zhang 012; Hai Li 001; Bingsheng He (MCSoC, 2015)

Leveraging Hotspots and Improving Chip Reliability via Carbon Nanotube Grid Thermal Structure. - Hao Liang 003; Wei Zhang 012; Jiale Huang; Shengqi Yang; Pallav Gupta (IEEE Trans. Very Large Scale Integr. Syst., 2015)

FDR 2.0: A Low-Power Dynamically Reconfigurable Architecture and Its FinFET Implementation. - Ting-Jung Lin; Wei Zhang 012; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC. - Xuan Wang 001; Jiang Xu 001; Wei Zhang 012; Xiaowen Wu; Yaoyao Ye; Zhehui Wang; Mahdi Nikdast; Zhe Wang 003 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Analytical Delay Model for CPU-FPGA Data Paths in Programmable System-on-Chip FPGA. - Mohammad Tahghighi; Sharad Sinha; Wei Zhang 012 (ARC, 2016)

A racetrack memory based in-memory booth multiplier for cryptography application. - Tao Luo 014; Wei Zhang 012; Bingsheng He; Douglas L. Maskell (ASP-DAC, 2016)

A discrete thermal controller for chip-multiprocessors. - Yingnan Cui; Wei Zhang 012; Bingsheng He (DATE, 2016)

Accelerating Database Query Processing on OpenCL-based FPGAs (Abstract Only). - Ze-ke Wang; Hui Yan Cheah; Johns Paul; Bingsheng He; Wei Zhang 012 (FPGA, 2016)

Relational query processing on OpenCL-based FPGAs. - Ze-ke Wang; Johns Paul; Hui Yan Cheah; Bingsheng He; Wei Zhang 012 (FPL, 2016)

Modular Placement for Interposer based Multi-FPGA Systems. - Fubing Mao; Wei Zhang 012; Bo Feng; Bingsheng He; Yuchun Ma (ACM Great Lakes Symposium on VLSI, 2016)

A performance analysis framework for optimizing OpenCL applications on FPGAs. - Ze-ke Wang; Bingsheng He; Wei Zhang 012; Shunning Jiang (HPCA, 2016)

Online malware defense using attack behavior model. - Sanjeev Das; Hao Xiao; Yang Liu 003; Wei Zhang 012 (ISCAS, 2016)

Area Efficient Hardware Architecture for Implicitly-Defined Complex Events Processing. - Mohammad Tahghighi; Wei Zhang 012; Sharad Sinha (ISVLSI, 2016)

Thermal-Aware Task Scheduling for 3D-Network-on-Chip: A Bottom to Top Scheme. - Yingnan Cui; Wei Zhang 012; Vivek Chaturvedi; Weichen Liu; Bingsheng He (J. Circuits Syst. Comput., 2016)

Cost-efficient Acceleration of Hardware Trojan Detection Through Fan-Out Cone Analysis and Weighted Random Pattern Technique. - Bin Zhou; Wei Zhang 012; Thambipillai Srikanthan; Jason Teo Kian Jin; Vivek Chaturvedi; Tao Luo 014 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Semantics-Based Online Malware Detection: Towards Efficient Real-Time Protection Against Malware. - Sanjeev Das; Yang Liu 003; Wei Zhang 012; Mahinthan Chandramohan (IEEE Trans. Inf. Forensics Secur., 2016)

Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration. - Fubing Mao; Yi-Chung Chen; Wei Zhang 012; Hai (Helen) Li; Bingsheng He (ACM Trans. Design Autom. Electr. Syst., 2016)

Melia: A MapReduce Framework on OpenCL-Based FPGAs. - Ze-ke Wang; Shuhao Zhang 001; Bingsheng He; Wei Zhang 012 (IEEE Trans. Parallel Distributed Syst., 2016)

Decentralized Thermal-Aware Task Scheduling for Large-Scale Many-Core Systems. - Yingnan Cui; Wei Zhang 012; Vivek Chaturvedi; Bingsheng He (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A Fine-Grained Control Flow Integrity Approach Against Runtime Memory Attacks for Embedded Systems. - Sanjeev Das; Wei Zhang 012; Yang Liu 003 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip. - Weichen Liu; Wei Zhang 012; Xuan Wang 001; Jiang Xu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Low-Power FPGA Design Using Memoization-Based Approximate Computing. - Sharad Sinha; Wei Zhang 012 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Two-stage thermal-aware scheduling of task graphs on 3D multi-cores exploiting application and architecture characteristics. - Zuomin Zhu; Vivek Chaturvedi; Amit Kumar Singh 002; Wei Zhang 012; Yingnan Cui (ASP-DAC, 2017)

No-Jump-into-Basic-Block: Enforce Basic Block CFI on the Fly for Real-world Binaries. - Wenjian He; Sanjeev Das; Wei Zhang 012; Yang Liu 003 (DAC, 2017)

FlexCL: An Analytical Performance Model for OpenCL Workloads on Flexible FPGAs. - Shuo Wang 009; Yun Liang 001; Wei Zhang 012 (DAC, 2017)

FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates. - Yijin Guan; Hao Liang 003; Ningyi Xu; Wenqiang Wang; Shaoshuai Shi; Xi Chen 107; Guangyu Sun 003; Wei Zhang 012; Jason Cong (FCCM, 2017)

Dynamic Module Partitioning for Library Based Placement on Heterogeneous FPGAs. - Fubing Mao; Wei Zhang 012; Bingsheng He; SiewKei Lam (FCCM, 2017)

Dynamic Partitioning for Library based Placement on Heterogeneous FPGAs (Abstract Only). - Fubing Mao; Wei Zhang 012; Bingsheng He; SiewKei Lam (FPGA, 2017)

PAAS: A system level simulator for heterogeneous computing architectures. - Tingyuan Liang; Liang Feng 001; Sharad Sinha; Wei Zhang 012 (FPL, 2017)

Decision tree based hardware power monitoring for run time dynamic power management in FPGA. - Zhe Lin 007; Wei Zhang 012; Sharad Sinha (FPL, 2017)

A hybrid approach to cache management in heterogeneous CPU-FPGA platforms. - Liang Feng 001; Sharad Sinha; Wei Zhang 012; Yun Liang 001 (ICCAD, 2017)

A novel two-stage modular multiplier based on racetrack memory for asymmetric cryptography. - Tao Luo 014; Bingsheng He; Wei Zhang 012; Douglas L. Maskell (ICCAD, 2017)

COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications. - Jieru Zhao; Liang Feng 001; Sharad Sinha; Wei Zhang 012; Yun Liang 001; Bingsheng He (ICCAD, 2017)

HeteroSim: A Heterogeneous CPU-FPGA Simulator. - Liang Feng 001; Hao Liang 003; Sharad Sinha; Wei Zhang 012 (IEEE Comput. Archit. Lett., 2017)

Fracturable DSP Block for Multi-context Reconfigurable Architectures. - Rakesh Warrier; Shanker Shreejith; Wei Zhang 012; Chan Hua Vun; Suhaib A. Fahmy (Circuits Syst. Signal Process., 2017)

Pipeline Reconfigurable DSP for Dynamically Reconfigurable Architectures. - Rakesh Warrier; Wei Zhang 012; Chan Hua Vun (Circuits Syst. Signal Process., 2017)

Local-to-global background modeling for moving object detection from non-static cameras. - Aihua Zheng; Lei Zhang 074; Wei Zhang 012; Chenglong Li 002; Jin Tang 001; Bin Luo 001 (Multim. Tools Appl., 2017)

A Hybrid Logic Block Architecture in FPGA for Holistic Efficiency. - Tao Luo 014; Hao Liang 003; Wei Zhang 012; Bingsheng He; Douglas L. Maskell (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Editorial. - Krishnendu Chakrabarty; Massimo Alioto; Bevan M. Baas; Chirn Chye Boon; Meng-Fan Chang; Naehyuck Chang; Yao-Wen Chang; Chip-Hong Chang; Shih-Chieh Chang; Poki Chen; Masud H. Chowdhury; Pasquale Corsonello; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Variation-Aware Adaptive Fuzzy Control System for Thermal Management of Microprocessors. - Yingnan Cui; Wei Zhang 012; Bingsheng He (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Multikernel Data Partitioning With Channel on OpenCL-Based FPGAs. - Ze-ke Wang; Johns Paul; Bingsheng He; Wei Zhang 012 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

CAMAS: Static and Dynamic Hybrid Cache Management for CPU-FPGA Platforms. - Liang Feng 001; Sharad Sinha; Wei Zhang 012; Yun Liang 001 (FCCM, 2018)

A Collaborative Framework for FPGA-based CNN Design Modeling and Optimization. - Jiandong Mu; Wei Zhang 012; Hao Liang 003; Sharad Sinha (FPL, 2018)

SGXlinger: A New Side-Channel Attack Vector Based on Interrupt Latency Against Enclave Execution. - Wenjian He; Wei Zhang 012; Sanjeev Das; Yang Liu 003 (ICCD, 2018)

ROPSentry: Runtime defense against ROP attacks using hardware performance counters. - Sanjeev Das; Bihuan Chen 001; Mahinthan Chandramohan; Yang Liu 003; Wei Zhang 012 (Comput. Secur., 2018)

FlexCL: A Model of Performance and Power for OpenCL Workloads on FPGAs. - Yun Liang 001; Shuo Wang 009; Wei Zhang 012 (IEEE Trans. Computers, 2018)

Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip. - Weichen Liu; Lei Yang 018; Weiwen Jiang; Liang Feng 001; Nan Guan; Wei Zhang 012; Nikil D. Dutt (IEEE Trans. Computers, 2018)

Parallelizing Hardware Tasks on Multicontext FPGA With Efficient Placement and Scheduling Algorithms. - Hao Liang 003; Sharad Sinha; Wei Zhang 012 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis. - Tingyuan Liang; Jieru Zhao; Liang Feng 001; Sharad Sinha; Wei Zhang 012 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors. - Zhe Lin 007; Sharad Sinha; Hao Liang 003; Liang Feng 001; Wei Zhang 012 (IEEE Trans. Multi Scale Comput. Syst., 2018)

Real-Time Detection and Tracking Using Hybrid DNNs and Space-Aware Color Feature: From Algorithm to System. - Liang Feng 001; Hiroaki Igarashi; Seiya Shibata; Yuki Kobayashi; Takashi Takenaka; Wei Zhang 012 (ACPR (1), 2019)

Accelerate pattern recognition for cyber security analysis. - Mohammad Tahghighi; Wei Zhang 012 (ASP-DAC, 2019)

LAMA: Link-Aware Hybrid Management for Memory Accesses in Emerging CPU-FPGA Platforms. - Liang Feng 001; Jieru Zhao; Tingyuan Liang; Sharad Sinha; Wei Zhang 012 (DAC, 2019)

Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis. - Jieru Zhao; Tingyuan Liang; Sharad Sinha; Wei Zhang 012 (DATE, 2019)

Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA. - Zhe Lin 007; Sharad Sinha; Wei Zhang 012 (FCCM, 2019)

A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA Platforms. - Liang Feng 001; Jieru Zhao; Tingyuan Liang; Sharad Sinha; Wei Zhang 012 (FPGA, 2019)

Poly: Efficient Heterogeneous System and Application Management for Interactive Applications. - Shuo Wang 009; Yun Liang 001; Wei Zhang 012 (HPCA, 2019)

Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis. - Tingyuan Liang; Jieru Zhao; Liang Feng 001; Sharad Sinha; Wei Zhang 012 (ICCAD, 2019)

A Cost-Effective CNN Accelerator Design with Configurable PU on FPGA. - Chi Fung Brian Fong; Jiandong Mu; Wei Zhang 012 (ISVLSI, 2019)

An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power. - Zhe Lin 007; Sharad Sinha; Wei Zhang 012 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Two-Layer Distributed Formation-Containment Control of Multiple Euler-Lagrange Systems by Output Feedback. - Dongyu Li; Wei Zhang 012; Wei He 001; Chuanjiang Li; Shuzhi Sam Ge (IEEE Trans. Cybern., 2019)

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. - Massimo Alioto; Magdy S. Abadir; Tughrul Arslan; Chirn Chye Boon; Andreas Burg 001; Chip-Hong Chang; Meng-Fan Chang; Yao-Wen Chang; Poki Chen; Pasquale Corsonello; Paolo Crovetti; Shiro Dosho; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2019)

HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis. - Zhe Lin 007; Jieru Zhao; Sharad Sinha; Wei Zhang 012 (ASP-DAC, 2020)

iGPU Leak: An Information Leakage Vulnerability on Intel Integrated GPU. - Wenjian He; Wei Zhang 012; Sharad Sinha; Sanjeev Das (ASP-DAC, 2020)

A History-Based Auto-Tuning Framework for Fast and High-Performance DNN Design on GPU. - Jiandong Mu; Mengdi Wang; Lanbo Li; Jun Yang 052; Wei Lin 016; Wei Zhang 012 (DAC, 2020)

Boyi: A Systematic Framework for Automatically Deciding the Right Execution Model of OpenCL Applications on FPGAs. - Jiantong Jiang; Zeke Wang; Xue Liu 003; Juan Gómez-Luna; Nan Guan; Qingxu Deng; Wei Zhang 012; Onur Mutlu (FPGA, 2020)

FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications. - Jieru Zhao; Tingyuan Liang; Liang Feng 001; Wenchao Ding 001; Sharad Sinha; Wei Zhang 012; Shaojie Shen (FPL, 2020)

Energy Efficient In-memory Integer Multiplication Based on Racetrack Memory. - Tao Luo 014; Wei Zhang 012; Bingsheng He; Cheng Liu 008; Douglas L. Maskell (ICDCS, 2020)

NCPower: Power Modelling for NVM-based Neuromorphic Chip. - Zhehui Wang; Huaipeng Zhang; Tao Luo 014; Weng-Fai Wong; Anh-Tuan Do; Paramasivam Vishnu; Wei Zhang 012; Rick Siow Mong Goh (ICONS, 2020)

Development of a navigation performance evaluation system. - Fangfang Zhao; Wei Zhang 012; Shuzhi Sam Ge (Sci. China Inf. Sci., 2020)

Introduction to the Special Issue on New Trends in Nanoelectronic Device, Circuit, and Architecture Design, Part 1. - Hai Helen Li; Wei Zhang 012; Swarup Bhunia; Wujie Wen (ACM J. Emerg. Technol. Comput. Syst., 2020)

Guest Editorial: ACM JETC Special Issue on New Trends in Nanolectronic Device, Circuit, and Architecture Design: Part 2. - Wei Zhang 012; Hai Helen Li; Wujie Wen; Swarup Bhunia (ACM J. Emerg. Technol. Comput. Syst., 2020)

Performance Modeling and Directives Optimization for High-Level Synthesis on FPGA. - Jieru Zhao; Liang Feng 001; Sharad Sinha; Wei Zhang 012; Yun Liang 001; Bingsheng He (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Energy Minimization for Multicore Platforms Through DVFS and VR Phase Scaling With Comprehensive Convex Model. - Zuomin Zhu; Wei Zhang 012; Vivek Chaturvedi; Amit Kumar Singh 002 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

BBB-CFI: Lightweight CFI Approach Against Code-Reuse Attacks Using Basic Block Information. - Wenjian He; Sanjeev Das; Wei Zhang 012; Yang Liu 003 (ACM Trans. Embed. Comput. Syst., 2020)

Optimizing OpenCL-Based CNN Design on FPGA with Comprehensive Design Space Exploration and Collaborative Performance Modeling. - Jiandong Mu; Wei Zhang 012; Hao Liang 003; Sharad Sinha (ACM Trans. Reconfigurable Technol. Syst., 2020)

Load-Step: A Precise TrustZone Execution Control Framework for Exploring New Side-channel Attacks Like Flush+Evict. - Zili Kou; Wenjian He; Sharad Sinha; Wei Zhang 012 (DAC, 2021)

Graph Sampling with Fast Random Walker on HBM-enabled FPGA Accelerators. - Chunyou Su; Hao Liang 003; Wei Zhang 012; Kun Zhao; Baole Ai; Wenting Shen; Zeke Wang (FPL, 2021)

Concentration Gradients Enhancement of Christmas-Tree Structure Based on a Look-Up Table. - Wei Zhang 012; Yongxiao Zhou; Tsung-Yi Ho; Hailong Yao (ACM Great Lakes Symposium on VLSI, 2021)

AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA. - Tingyuan Liang; Gengjie Chen; Jieru Zhao; Sharad Sinha; Wei Zhang 012 (ICCAD, 2021)

TCL: Transformer-based Dynamic Graph Modelling via Contrastive Learning. - Lu Wang 029; Xiaofu Chang; Shuang Li 002; Yunfei Chu; Hui Li 061; Wei Zhang 012; Xiaofeng He; Le Song; Jingren Zhou 001; Hongxia Yang (CoRR, 2021)

High-dimensional Bayesian Optimization for CNN Auto Pruning with Clustering and Rollback. - Jiandong Mu; Hanwei Fan; Wei Zhang 012 (CoRR, 2021)

Fangorn: Adaptive Execution Framework for Heterogeneous Workloads on Shared Clusters. - Yingda Chen; Jiamang Wang; Yifeng Lu; Ying Han; Zhiqiang Lv; Xuebin Min; Hua Cai; Wei Zhang 012; Haochuan Fan; Chao Li 009; Tao Guan; Wei Lin 016; et al. (Proc. VLDB Endow., 2021)

Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System. - Zhe Lin 007; Sharad Sinha; Wei Zhang 012 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs. - Zhe Lin 007; Zike Yuan; Jieru Zhao; Wei Zhang 012; Hui Wang 030; Yonghong Tian 001 (DATE, 2022)

Bayesian Optimization with Clustering and Rollback for CNN Auto Pruning. - Hanwei Fan; Jiandong Mu; Wei Zhang 012 (ECCV (23), 2022)

Preface. - Yun Liang 001; Hiroki Nakahara; Wei Zhang 012; Fubing Mao; Ray C. C. Cheung (FPT, 2022)

Message from the General Chair and Program Co-Chairs. - Wei Zhang 012; Ray C. C. Cheung; Yun Liang 001; Hiroki Nakahara (FPT, 2022)

Attack Directories on ARM big.LITTLE Processors. - Zili Kou; Sharad Sinha; Wenjian He; Wei Zhang 012 (ICCAD, 2022)

AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining. - Tingyuan Liang; Jingsong Chen; Lei Li; Wei Zhang 012 (CoRR, 2022)

Introduction to the Special Issue on Hardware-Assisted Security for Emerging Internet of Things. - Saraju P. Mohanty; Jim Plusquellic; Garrett S. Rose; Wei Zhang 012; Maria K. Michael (ACM J. Emerg. Technol. Comput. Syst., 2022)

Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems. - Benjamin Chen Ming Choong; Tao Luo 014; Cheng Liu 008; Bingsheng He; Wei Zhang 012; Joey Tianyi Zhou (J. Syst. Archit., 2022)

PertNAS: Architectural Perturbations for Memory-Efficient Neural Architecture Search. - Afzal Ahmad; Zhiyao Xie; Wei Zhang 012 (DAC, 2023)

ACGraph: Accelerating Streaming Graph Processing via Dependence Hierarchy. - Zihan Jiang; Fubing Mao; Yapu Guo; Xu Liu; Haikun Liu; Xiaofei Liao; Hai Jin 001; Wei Zhang 012 (DAC, 2023)

PROPHET: Predictive On-Chip Power Meter in Hardware Accelerator for DNN. - Jian Peng; Tingyuan Liang; Zhiyao Xie; Wei Zhang 012 (DAC, 2023)

Cache Side-channel Attacks and Defenses of the Sliding Window Algorithm in TEEs. - Zili Kou; Sharad Sinha; Wenjian He; Wei Zhang 012 (DATE, 2023)

Tensor-Product-Based Accelerator for Area-efficient and Scalable Number Theoretic Transform. - Yuying Zhang; Sathi Sarveswara Reddy; Zili Kou; Sharad Sinha; Wei Zhang 012 (FCCM, 2023)

FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs. - Linfeng Du; Tingyuan Liang; Sharad Sinha; Zhiyao Xie; Wei Zhang 012 (FPGA, 2023)

DiffLo: A Graph-based Method for Functional Discrepancy Localization in High-level Synthesis. - Liangji Chen; Tingyuan Liang; Wei Zhang 012; Sharad Sinha (ICFPT, 2023)

FIONA: Photonic-Electronic CoSimulation Framework and Transferable Prototyping for Photonic Accelerator. - Yinyi Liu; Bohan Hu; Zhenguo Liu; Peiyu Chen; Linfeng Du; Jiaqi Liu; Xianbin Li; Wei Zhang 012; Jiang Xu 001 (ICCAD, 2023)

NeuroPDR: Integrating Neural Networks in the PDR Algorithm for Hardware Model Checking. - Guangyu Hu; Wei Zhang 012; Hongce Zhang (MLCAD, 2023)

Introduction to the Special Issue on FPT 2021. - Andreas Koch 001; Wei Zhang 012 (ACM Trans. Reconfigurable Technol. Syst., 2023)

Design and Analysis of RSA and Paillier Homomorphic Cryptosystems Using PSO-Based Evolutionary Computation. - Sathi Sarveswara Reddy; Sharad Sinha; Wei Zhang 012 (IEEE Trans. Computers, 2023)

HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS. - Zhe Lin 007; Tingyuan Liang; Jieru Zhao; Sharad Sinha; Wei Zhang 012 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Special Issue: "AI Acceleration on FPGAs". - Yun Liang 001; Wei Zhang 012; Stephen Neuendorffer; Wayne Luk (ACM Trans. Embed. Comput. Syst., 2023)

Accelerating Loop-Oriented RTL Simulation With Code Instrumentation. - Fubing Mao; Yapu Guo; Xiaofei Liao; Hai Jin 001; Wei Zhang 012; Haikun Liu; Long Zheng 003; Xu Liu; Zihan Jiang; Xiaohua Zheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction. - Guangyu Hu; Jianheng Tang; Changyuan Yu; Wei Zhang 012; Hongce Zhang (ASPDAC, 2024)

Accel-NASBench: Sustainable Benchmarking for Accelerator-Aware NAS. - Afzal Ahmad; Linfeng Du; Zhiyao Xie; Wei Zhang 012 (DAC, 2024)

Explainable Fuzzy Neural Network with Multi-Fidelity Reinforcement Learning for Micro-Architecture Design Space Exploration. - Hanwei Fan; Ya Wang; Sicheng Li 001; Tingyuan Liang; Wei Zhang 012 (DAC, 2024)

PhotonNTT: Energy-Efficient Parallel Photonic Number Theoretic Transform Accelerator. - Xianbin Li; Jiaqi Liu; Yuying Zhang; Yinyi Liu; Jiaxu Zhang; Chengeng Li; Shixi Chen; Yuxiang Fu; Fengshi Tian; Wei Zhang 012; Jiang Xu 001 (DATE, 2024)

A Modular Branch Predictor Performance Analysis Framework for Fast Design Space Exploration. - Ya Wang; Hanwei Fan; Sicheng Li 001; Tingyuan Liang; Wei Zhang 012 (DATE, 2024)

GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network. - Chunyou Su; Linfeng Du; Tingyuan Liang; Zhe Lin 007; Maolin Wang 002; Sharad Sinha; Wei Zhang 012 (FPGA, 2024)

LCM: LLM-focused Hybrid SPM-cache Architecture with Cache Management for Multi-Core AI Accelerators. - Chengtao Lai; Zhongchun Zhou; Akash Poptani; Wei Zhang 012 (ICS, 2024)

NEOCNN: NTT-Enabled Optical Convolution Neural Network Accelerator. - Xianbin Li; Yinyi Liu; Fan Jiang; Chengeng Li; Yuxiang Fu; Wei Zhang 012; Jiang Xu 001 (ICS, 2024)

PC-oriented Prediction-based Runtime Power Management for GPGPU using Knowledge Transfer. - Lin Chen 029; Xiao Li; Shixi Chen; Fan Jiang; Chengeng Li; Wei Zhang 012; Jiang Xu 001 (SPAA, 2024)

Retain, Blend, and Exchange: A Quality-aware Spatial-Stereo Fusion Approach for Event Stream Recognition. - Lan Chen; Dong Li; Xiao Wang 014; Pengpeng Shao; Wei Zhang 012; Yaowei Wang 001; Yonghong Tian 001; Jin Tang 001 (CoRR, 2024)

MS-Mapping: An Uncertainty-Aware Large-Scale Multi-Session LiDAR Mapping System. - Xiangcheng Hu; Jin Wu 002; Jianhao Jiao; Binqian Jiang; Wei Zhang 012; Wenshuo Wang 001; Ping Tan (CoRR, 2024)

Dual-AEB: Synergizing Rule-Based and Multimodal Large Language Models for Effective Emergency Braking. - Wei Zhang 012; Pengfei Li; Junli Wang; Bingchuan Sun; Qihao Jin; Guangjun Bao; Shibo Rui; Yang Yu; Wenchao Ding 001; Peng Li; Yilun Chen (CoRR, 2024)

gem5-NVDLA: A Simulation Framework for Compiling, Scheduling, and Architecture Evaluation on AI System-on-Chips. - Chengtao Lai; Wei Zhang 012 (ACM Trans. Design Autom. Electr. Syst., 2024)

Boosting the Convergence of Reinforcement Learning-Based Auto-Pruning Using Historical Data. - Jiandong Mu; Mengdi Wang; Feiwen Zhu; Jun Yang 052; Wei Lin 016; Wei Zhang 012 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Unveiling the Advantages of Full Coherency Architecture for FPSoC Systems. - Enlai Li; Sharad Sinha; Wei Zhang 012 (IEEE Trans. Very Large Scale Integr. Syst., 2024)

AMF-Placer 2.0: Open-Source Timing-Driven Analytical Mixed-Size Placer for Large-Scale Heterogeneous FPGA. - Tingyuan Liang; Gengjie Chen; Jieru Zhao; Sharad Sinha; Wei Zhang 012 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs. - Linfeng Du; Tingyuan Liang; Xiaofeng Zhou; Jinming Ge; Shangkun Li; Sharad Sinha; Jieru Zhao; Zhiyao Xie; Wei Zhang 012 (ACM Trans. Reconfigurable Technol. Syst., 2024)

Deep Reinforcement Learning-Based Power Management for Chiplet-Based Multicore Systems. - Xiao Li; Lin Chen 029; Shixi Chen; Fan Jiang; Chengeng Li; Wei Zhang 012; Jiang Xu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Optimizing for In-Memory Deep Learning With Emerging Memory Technology. - Zhehui Wang; Tao Luo 014; Rick Siow Mong Goh; Wei Zhang 012; Weng-Fai Wong (IEEE Trans. Neural Networks Learn. Syst., 2024)

PMGraph: Accelerating Concurrent Graph Queries over Streaming Graphs. - Fubing Mao; Xu Liu; Yu Zhang 027; Haikun Liu; Xiaofei Liao; Hai Jin 001; Wei Zhang 012; Jian Zhou; Yufei Wu 024; Longyu Nie; Yapu Guo; Zihan Jiang; et al. (ACM Trans. Archit. Code Optim., 2024)

Data-Pattern-Based Predictive On-Chip Power Meter in DNN Accelerator. - Jian Peng; Tingyuan Liang; Jingbo Jiang; Yipu Zhang; Zhe Lin 007; Zhiyao Xie; Wei Zhang 012 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

SpNeRF: Memory Efficient Sparse Volumetric Neural Rendering Accelerator for Edge Devices. - Yipu Zhang; Jiawei Liang; Jian Peng; Jiang Xu 001; Wei Zhang 012 (DATE, 2025)

TAPCA: An Interface-Aware Cache Management Framework for Task Partitioning on CPU-FPGA SoC Platforms. - Enlai Li; Zhe Lin 007; Sharad Sinha; Wei Zhang 012 (FPGA, 2025)

Reflectance-Guided Progressive Feature Alignment Network for All-Day UAV Object Detection. - Zhicheng Zhao 002; Wei Zhang 012; Yun Xiao 003; Chenglong Li 002; Jin Tang 001 (IEEE Trans. Geosci. Remote. Sens., 2025)

AM-Align: Globally Optimal Estimation of Accelerometer-Magnetometer Misalignment. - Xiangcheng Hu; Jin Wu 002; Bohuan Xue; Yilong Zhu; Mingkai Jia; Yuhua Qi; Yi Jiang 007; Ping Tan; Wei Zhang 012 (IEEE Trans. Instrum. Meas., 2025)

On Similarity Transformation Problems: Globally Optimal Results and Applications. - Jin Wu 002; Chaoqun Wang 009; Chong Li 006; Yi Jiang 007; Chengxi Zhang; Yulong Huang; Yuhua Qi; Bohuan Xue; Jianhao Jiao; Rui Fan 001; Wei Zhang 012 (IEEE Trans. Instrum. Meas., 2025)

MapEval: Towards Unified, Robust and Efficient SLAM Map Evaluation Framework. - Xiangcheng Hu; Jin Wu 002; Mingkai Jia; Hongyu Yan; Yi Jiang 007; Binqian Jiang; Wei Zhang 012; Wei He 001; Ping Tan (IEEE Robotics Autom. Lett., 2025)

A Pseudo Global Fusion Paradigm-Based Cross-View Network for LiDAR-Based Place Recognition. - Jintao Cheng; Jiehao Luo; Xieyuanli Chen; Jin Wu 002; Rui Fan 001; Xiaoyu Tang; Wei Zhang 012 (CoRR, 2025)

UMD-Net: A Unified Multi-Task Assistive Driving Network Based on Multimodal Fusion. - Wenzhuo Liu; Yicheng Qiao; Zhiwei Li; Wenshuo Wang 001; Wei Zhang 012; Jiayin Zhu; Yanhuan Jiang; Li Wang 092; Hong Wang 014; Huaping Liu 001; Kunfeng Wang (IEEE Trans. Intell. Transp. Syst., 2025)