An SRAM reliability test macro for fully-automated statistical measurements of Vmin degradation. - Tony Tae-Hyoung Kim; Wei Zhang 032; Chris H. Kim (CICC, 2009)

Variation aware performance analysis of gain cell embedded DRAMs. - Wei Zhang 032; Ki Chul Chun; Chris H. Kim (ISLPED, 2010)

A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted supplies. - Ki Chul Chun; Wei Zhang 032; Pulkit Jain; Chris H. Kim (ISSCC, 2011)

A 1V printed organic DRAM cell based on ion-gel gated transistors with a sub-10nW-per-cell Refresh Power. - Wei Zhang 032; Mingjing Ha; Daniele Braga; Michael J. Renn; C. Daniel Frisbie; Chris H. Kim (ISSCC, 2011)

An Array-Based Odometer System for Statistically Significant Circuit Aging Characterization. - John Keane 001; Wei Zhang 032; Chris H. Kim (IEEE J. Solid State Circuits, 2011)

A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor. - Ki Chul Chun; Wei Zhang 032; Pulkit Jain; Chris H. Kim (IEEE J. Solid State Circuits, 2012)

An SRAM Reliability Test Macro for Fully Automated Statistical Measurements of VMIN Degradation. - Tony Tae-Hyoung Kim; Wei Zhang 032; Chris H. Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A Write-Back-Free 2T1D Embedded DRAM With Local Voltage Sensing and a Dual-Row-Access Low Power Mode. - Wei Zhang 032; Ki Chul Chun; Chris H. Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)