An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and -252 dB FoM. - Weichen Tao; Weichen Zhao; Robert Bogdan Staszewski; Fujiang Lin; Yizhe Hu (VLSI Technology and Circuits, 2023)

A First Look at the Impact of Measurement on Orchestrating Digital Twin Network. - Weichen Tao; Leonardo Linguaglossa (CloudNet, 2024)

A 25-GHz PLL Achieving 8-ns Phase-Shifting Time With Double-Path Modulation Scheme. - Weichen Zhao; Weichen Tao; Yongheng Liu; Jingyuan Zhang; Zhongjun Zhang; Xu Yan 006; C. Patrick Yue; Fujiang Lin (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A Charge-Domain Fractional-N ADPLL Based on Charge-Steering Sampling. - Weichen Tao; Yuhao Yang; Weiyi Chen; Robert Bogdan Staszewski; Yizhe Hu (IEEE J. Solid State Circuits, 2025)