A 40Gb/s 39mW 3-tap adaptive closed-loop decision feedback equalizer in 65nm CMOS. - Weidong Cao 001; Ziqiang Wang; Dongmei Li; Xuqiang Zheng; Fule Li; Chun Zhang; Zhihua Wang 001 (MWSCAS, 2015)

A 40Gb/s 27mW 3-tap closed-loop decision feedback equalizer in 65nm CMOS. - Weidong Cao 001; Ziqiang Wang; Dongmei Li; Xuqiang Zheng; Ke Huang 003; Shuai Yuan 005; Fule Li; Zhihua Wang 001 (NEWCAS, 2015)

A 28-Gb/s transmitter with 3-tap FFE and T-coil enhanced terminal in 65-nm CMOS technology. - Naiwen Zhou; Linghan Wu; Ziqiang Wang; Xuqiang Zheng; Weidong Cao 001; Chun Zhang; Fule Li; Zhihua Wang 001 (NEWCAS, 2016)

A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications. - Fangxu Lv; Xuqiang Zheng; Feng Zhao 004; Jianye Wang; Shigang Yue; Ziqiang Wang; Weidong Cao 001; Yajun He; Chun Zhang; Hanjun Jiang; Zhihua Wang 001 (Microelectron. J., 2018)

NeuADC: Neural Network-Inspired RRAM-Based Synthesizable Analog-to-Digital Conversion with Reconfigurable Quantization Support. - Weidong Cao 001; Xin He; Ayan Chakrabarti; Xuan Zhang 001 (DATE, 2019)

Neural Network-Inspired Analog-to-Digital Conversion to Achieve Super-Resolution with Low-Precision RRAM Devices. - Weidong Cao 001; Liu Ke 001; Ayan Chakrabarti; Xuan Zhang 001 (ICCAD, 2019)

NeuADC: Neural Network-Inspired Synthesizable Analog-to-Digital Conversion. - Weidong Cao 001; Xin He; Ayan Chakrabarti; Xuan Zhang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Evaluating Neural Network-Inspired Analog-to-Digital Conversion With Low-Precision RRAM. - Weidong Cao 001; Liu Ke 001; Ayan Chakrabarti; Xuan Zhang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Domain knowledge-infused deep learning for automated analog/radio-frequency circuit parameter optimization. - Weidong Cao 001; Mouhacine Benosman; Xuan Zhang 001; Rui Ma (DAC, 2022)

PowerTouch: A Security Objective-Guided Automation Framework for Generating Wired Ghost Touch Attacks on Touchscreens. - Huifeng Zhu; Zhiyuan Yu 001; Weidong Cao 001; Ning Zhang 017; Xuan Zhang 001 (ICCAD, 2022)

HOGEye: Neural Approximation of HOG Feature Extraction in RRAM-Based 3D-Stacked Image Sensors. - Tianrui Ma; Weidong Cao 001; Fei Qiao; Ayan Chakrabarti; Xuan Zhang 001 (ISLPED, 2022)

Domain Knowledge-Based Automated Analog Circuit Design with Deep Reinforcement Learning. - Weidong Cao 001; Mouhacine Benosman; Xuan Zhang 001; Rui Ma (CoRR, 2022)

Demonstration of fully integrated parity-time-symmetric electronics. - Weidong Cao 001; Changqing Wang; Weijian Chen; Song Hu; Hua Wang; Lan Yang 005; Xuan Zhang 001 (CoRR, 2022)

Neural-PIM: Efficient Processing-In-Memory With Neural Approximation of Peripherals. - Weidong Cao 001; Yilong Zhao; Adith Boloor; Yinhe Han 001; Xuan Zhang 001; Li Jiang 002 (IEEE Trans. Computers, 2022)

RoSE: Robust Analog Circuit Parameter Optimization with Sampling-Efficient Reinforcement Learning. - Jian Gao; Weidong Cao 001; Xuan Zhang 001 (DAC, 2023)

PDNSig: Identifying Multi-Tenant Cloud FPGAs with Power Distribution Network-Based Signatures. - Huifeng Zhu; Weidong Cao 001; Xuan Zhang 001 (ICCAD, 2023)

CktGNN: Circuit Graph Neural Network for Electronic Design Automation. - Zehao Dong; Weidong Cao 001; Muhan Zhang; Dacheng Tao; Yixin Chen 001; Xuan Zhang 001 (ICLR, 2023)

LeCA: In-Sensor Learned Compressive Acquisition for Efficient Machine Vision on the Edge. - Tianrui Ma; Adith Jagadish Boloor; Xiangxing Yang; Weidong Cao 001; Patrick Williams; Nan Sun 001; Ayan Chakrabarti; Xuan Zhang 001 (ISCA, 2023)

Non-Hermitian Physics-Inspired Voltage-Controlled Oscillators with Resistive Tuning. - Weidong Cao 001; Hua Wang; Xuan Zhang 001 (ISCAS, 2023)

A/D Alleviator: Reducing Analog-to-Digital Conversions in Compute-In-Memory with Augmented Analog Accumulation. - Weidong Cao 001; Xuan Zhang 001 (ISCAS, 2023)

Addition is Most You Need: Efficient Floating-Point SRAM Compute-in-Memory by Harnessing Mantissa Addition. - Weidong Cao 001; Jian Gao; Xin Xin 008; Xuan Zhang 001 (DAC, 2024)

Estimating Power, Performance, and Area for On-Sensor Deployment of AR/VR Workloads Using an Analytical Framework. - Xiaoyu Sun 001; Xiaochen Peng; Sai Qian Zhang; Jorge Gomez 002; Win-San Khwa; Syed Shakib Sarwar; Ziyun Li; Weidong Cao 001; Zhao Wang; Chiao Liu; Meng-Fan Chang; Barbara De Salvo; et al. (ACM Trans. Design Autom. Electr. Syst., 2024)

Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros. - Xiaoyu Sun 001; Weidong Cao 001; Brian Crafton; Kerem Akarvardar; Haruki Mori; Hidehiro Fujiwara; Hiroki Noguchi; Yu-Der Chih; Meng-Fan Chang; Yih Wang; Tsung-Yung Jonathan Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies. - Jian Gao; Weidong Cao 001; Junyi Yang; Xuan Zhang 001 (ICLR, 2025)

A Hybrid-Domain Floating-Point Compute-in-Memory Architecture for Efficient Acceleration of High-Precision Deep Neural Networks. - Zhiqiang Yi; Yiwen Liang; Weidong Cao 001 (CoRR, 2025)

RoSE-Opt: Robust and Efficient Analog Circuit Parameter Optimization With Knowledge-Infused Reinforcement Learning. - Weidong Cao 001; Jian Gao; Tianrui Ma; Rui Ma; Mouhacine Benosman; Xuan Zhang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)