An Efficient near-Bank Processing Architecture for Personalized Recommendation System. - Yuqing Yang; Weidong Yang 007; Qin Wang 009; Naifeng Jing; Jianfei Jiang 001; Zhigang Mao; Weiguang Sheng (ASP-DAC, 2023)

ACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors. - Shuya Ji; Weidong Yang 007; Jianfei Jiang 001; Naifeng Jing; Weiguang Sheng; Ang Li 045; Qin Wang 009 (ICCD, 2023)

RecPIM: Efficient In-Memory Processing for Personalized Recommendation Inference Using Near-Bank Architecture. - Weidong Yang 007; Yuqing Yang; Shuya Ji; Jianfei Jiang 001; Naifeng Jing; Qin Wang 009; Zhigang Mao; Weiguang Sheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

HEILP: An ILP-Based Scale Management Method for Homomorphic Encryption Compiler. - Weidong Yang 007; Shuya Ji; Jianfei Jiang 001; Naifeng Jing; Qin Wang 009; Zhigang Mao; Weiguang Sheng (DATE, 2025)

RVME: An Efficient Matrix Engine Design Based on Matrix Extension of RISC-V. - Wanqi Chen; Weidong Yang 007; Yiming Guo; Jing Qiu; Renpei Wang; Jianfei Jiang 001; Naifeng Jing; Qin Wang 009 (ICCD, 2025)

MACS: A Multidomain Collaborative Adaptive Clock Scheme for Large-Scale Reconfigurable Dataflow Accelerators. - Shuya Ji; Weidong Yang 007; Jianfei Jiang 001; Naifeng Jing; Honglan Jiang; Zhigang Mao; Qin Wang 009 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Viper: An ILP-Based Vectorization Framework for Fully Homomorphic Encryption. - Weidong Yang 007; Xinmo Li; Xiangmin Guo; Jianfei Jiang 001; Naifeng Jing; Qin Wang 009; Zhigang Mao; Weiguang Sheng (ASP-DAC, 2026)