Neuromorphic architectures with electronic synapses. - Sukru Burc Eryilmaz; Siddharth Joshi 001; Emre Neftci; Weier Wan; Gert Cauwenberghs; H.-S. Philip Wong (ISQED, 2016)

Coming Up N3XT, After 2D Scaling of Si CMOS. - William Hwang; Weier Wan; Subhasish Mitra; H.-S. Philip Wong (ISCAS, 2018)

A 1.52 pJ/Spike Reconfigurable Multimodal Integrate-and-Fire Neuron Array Transceiver. - Rajkumar Kubendran; Weier Wan; Siddharth Joshi 001; H.-S. Philip Wong; Gert Cauwenberghs (ICONS, 2020)

33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models. - Weier Wan; Rajkumar Kubendran; Sukru Burc Eryilmaz; Wenqiang Zhang; Yan Liao; Dabin Wu; Stephen R. Deiss; Bin Gao 006; Priyanka Raina; Siddharth Joshi 001; Huaqiang Wu; Gert Cauwenberghs; et al. (ISSCC, 2020)

Edge AI without Compromise: Efficient, Versatile and Accurate Neurocomputing in Resistive Random-Access Memory. - Weier Wan; Rajkumar Kubendran; Clemens J. S. Schaefer; Sukru Burc Eryilmaz; Wenqiang Zhang; Dabin Wu; Stephen R. Deiss; Priyanka Raina; He Qian; Bin Gao 006; Siddharth Joshi 001; Huaqiang Wu; et al. (CoRR, 2021)

A compute-in-memory chip based on resistive random-access memory. - Weier Wan; Rajkumar Kubendran; Clemens J. S. Schaefer; Sukru Burc Eryilmaz; Wenqiang Zhang; Dabin Wu; Stephen R. Deiss; Priyanka Raina; He Qian; Bin Gao 006; Siddharth Joshi 001; Huaqiang Wu; et al. (Nat., 2022)

PICO-RAM: A PVT-Insensitive Analog Compute-In-Memory SRAM Macro With In Situ Multi-Bit Charge Computing and 6T Thin-Cell-Compatible Layout. - Zhiyu Chen 003; Ziyuan Wen; Weier Wan; Akhil Reddy Pakala; Yiwei Zou; Wei-Chen Wei; Zengyi Li; Yubei Chen; Kaiyuan Yang 001 (IEEE J. Solid State Circuits, 2025)