An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling. - Weiguang Sheng; Liyi Xiao; Zhigang Mao (DELTA, 2008)

A novel soft error sensitivity characterization technique based on simulated fault injection and constrained association analysis. - Weiguang Sheng; Liyi Xiao; Zhigang Mao (ICECS, 2008)

Versatile and Efficient Techniques for Speeding-Up Circuit Level Simulated Fault-Injection Campaigns. - Weiguang Sheng; Liyi Xiao; Zhigang Mao (PRDC, 2008)

Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm. - Weiguang Sheng; Liyi Xiao; Zhigang Mao (DAC, 2009)

Automatic compilation flow for a coarse-grained reconfigurable processor. - Hao Wang; Weiguang Sheng; Weifeng He (ASICON, 2011)

Efficient temporal task partition for coarse-grain reconfigurable systems based on Simulated Annealing Genetic Algorithm. - Yifan Zhou; Weiguang Sheng; Xie Liu; Weifeng He; Zhigang Mao (ASICON, 2011)

A clock-less transceiver for global interconnect. - Jianfei Jiang 001; Xu Wang; Wei-Guang Sheng; Wei-Feng He; Zhi-Gang Mao (VLSI-SoC, 2011)

Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm. - Weiguang Sheng; Weifeng He; Jianfei Jiang 001; Zhigang Mao (IPDPS Workshops, 2012)

A pre-emphasis circuit design for high speed on-chip global interconnect. - Jianfei Jiang 001; Wei-Guang Sheng; Zhi-Gang Mao; Wei-Feng He (ISCAS, 2012)

Delay hidden techniques based on configuration contexts reuse and differential reconfiguration in coarse-grained reconfigurable processor. - Haopeng Liu; Weiguang Sheng; Weifeng He; Zhigang Mao (ASICON, 2013)

An automatic translation and parallelization system for general purpose reconfigurable processor. - Fengshuo Tian; Weiguang Sheng; Weifeng He (ASICON, 2015)

Designing ARINC653 Partition Constrained Scheduling for Secure Real Time Embedded Avionics. - Xiang Tao; Yongxin Zhu 001; Yishu Mao; Han Song; Mengyun Liu; Xinyi Liu; Weiguang Sheng; Weiwei Shi 002 (CSCloud, 2015)

A contactless testing methodology for pre-bond interposer. - Jianfei Jiang 001; Weiguang Sheng; Qin Wang 009; Zhigang Mao (MWSCAS, 2015)

Parasitic Parameters Impacts Investigation on Soft Error Rate by a Circuit Level Framework. - Weiguang Sheng; Zhongyuan Zhao 004; Zhigang Mao (PRDC, 2015)

Resource-saving compile flow for coarse-grained reconfigurable architectures. - Zhongyuan Zhao 004; Weiguang Sheng; Naifeng Jing; Weifeng He; Zhigang Mao (ReConFig, 2015)

Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects. - Jianfei Jiang 001; Zhigang Mao; Weiguang Sheng; Qin Wang 009; Weifeng He (J. Circuits Syst. Comput., 2016)

Parallel SER analysis for combinational and sequential standard cell circuits. - Weiguang Sheng; Jianfei Jiang 001; Zhigang Mao (Microelectron. J., 2016)

A static-placement, dynamic-issue framework for CGRA loop accelerator. - Zhongyuan Zhao 004; Weiguang Sheng; Weifeng He; Zhigang Mao; Zhaoshi Li (DATE, 2017)

Optimizing the data placement and transformation for multi-bank CGRA computing system. - Zhongyuan Zhao 004; Yantao Liu; Weiguang Sheng; Tushar Krishna; Qin Wang 009; Zhigang Mao (DATE, 2018)

Fail-Slow at Scale: Evidence of Hardware Performance Faults in Large Production Systems. - Haryadi S. Gunawi; Riza O. Suminto; Russell Sears; Casey Golliher; Swaminathan Sundararaman; Xing Lin; Tim Emami; Weiguang Sheng; Nematollah Bidokhti; Caitie McCaffrey; Gary Grider; Parks M. Fields; et al. (FAST, 2018)

MBSS: A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs. - Shuai Xie; Zhongyuan Zhao 004; Weiguang Sheng; Qin Wang 009; Zhigang Mao (ReConFig, 2018)

Fail-Slow at Scale: Evidence of Hardware Performance Faults in Large Production Systems. - Haryadi S. Gunawi; Riza O. Suminto; Russell Sears; Casey Golliher; Swaminathan Sundararaman; Xing Lin; Tim Emami; Weiguang Sheng; Nematollah Bidokhti; Caitie McCaffrey; Deepthi Srinivasan; Biswaranjan Panda; et al. (ACM Trans. Storage, 2018)

mRNA: Enabling Efficient Mapping Space Exploration for a Reconfiguration Neural Accelerator. - Zhongyuan Zhao 004; Hyoukjun Kwon; Sachit Kuhar; Weiguang Sheng; Zhigang Mao; Tushar Krishna (ISPASS, 2019)

Lung Nodule Detection in CT Images Using a Raw Patch-Based Convolutional Neural Network. - Qin Wang 009; Fengyi Shen; Linyao Shen; Jia Huang; Weiguang Sheng (J. Digit. Imaging, 2019)

A New Cellular-Based Redundant TSV Structure for Clustered Faults. - Qin Wang 009; Zechen Liu; Jianfei Jiang 001; Naifeng Jing; Weiguang Sheng (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration. - Zihan Zhang; Taozhong Li; Ning Guan; Qin Wang 009; Guanghui He; Weiguang Sheng; Zhigang Mao; Naifeng Jing (ACM Great Lakes Symposium on VLSI, 2020)

Priority Branches for Ship Detection in Optical Remote Sensing Images. - Yijia Zhang; Weiguang Sheng; Jianfei Jiang 001; Naifeng Jing; Qin Wang 009; Zhigang Mao (Remote. Sens., 2020)

Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling. - Zhongyuan Zhao 004; Weiguang Sheng; Qin Wang 009; Wenzhi Yin; Pengfei Ye; Jinchao Li; Zhigang Mao (IEEE Trans. Parallel Distributed Syst., 2020)

A Mapping Method for Reconfigurable Array based on Decoupled DataFlow. - Zihan Zhang; Jianfei Jiang 001; Weiguang Sheng; Qin Wang 009; Zhigang Mao; Naifeng Jing (BigDataSecurity, 2021)

Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture. - Yuge Chen; Zhongyuan Zhao 004; Jianfei Jiang 001; Guanghui He; Zhigang Mao; Weiguang Sheng (DATE, 2021)

Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture. - Chen Yin; Qin Wang 009; Jianfei Jiang 001; Weiguang Sheng; Guanghui He; Zhigang Mao; Naifeng Jing (DATE, 2021)

A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing. - Zhuojun Liang; Dongxu Lv; Chao Cui; Hai-Bao Chen; Weifeng He; Weiguang Sheng; Naifeng Jing; Zhigang Mao; Guanghui He (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A Low Coupling and Lightweight Algorithm for Ship Detection in Optical Remote Sensing Images. - Guochao Deng; Qin Wang 009; Jianfei Jiang 001; Qirun Hong; Naifeng Jing; Weiguang Sheng; Zhigang Mao (IEEE Geosci. Remote. Sens. Lett., 2022)

An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs. - Shengzhao Li; Qin Wang 009; Jianfei Jiang 001; Weiguang Sheng; Naifeng Jing; Zhigang Mao (IEEE Trans. Very Large Scale Integr. Syst., 2022)

ReMap: Reorder Mapping for Multi-level Uneven Distribution on Sparse ReRAM Accelerator. - Zhuo Chen; Zihan Zhang; Jianfei Jiang 001; Weiguang Sheng; Qin Wang 009; Naifeng Jing (ASICON, 2023)

An Efficient near-Bank Processing Architecture for Personalized Recommendation System. - Yuqing Yang; Weidong Yang; Qin Wang 009; Naifeng Jing; Jianfei Jiang 001; Zhigang Mao; Weiguang Sheng (ASP-DAC, 2023)

ACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors. - Shuya Ji; Weidong Yang; Jianfei Jiang 001; Naifeng Jing; Weiguang Sheng; Ang Li; Qin Wang 009 (ICCD, 2023)

RTMDet-R2: An Improved Real-Time Rotated Object Detector. - Haifeng Xiang; Naifeng Jing; Jianfei Jiang 001; Hongbo Guo; Weiguang Sheng; Zhigang Mao; Qin Wang 009 (PRCV (12), 2023)

VDA: A Simple but Efficient Virtual-Channel-Based Deadlock Avoidance Scheme for Scalable Chiplet Networks. - Duo Yu; Ang Li; Naifeng Jing; Jianfei Jiang 001; Weiguang Sheng; Qin Wang 009 (ACM Great Lakes Symposium on VLSI, 2024)

A Flexible and High-Precision Activation Function Unit Based on Equi-Error Partitioning Algorithm. - Zelong Yuan; Siwei Yuan; Pengyu Liu 004; Chen Yin; Lei Xu; Weiguang Sheng; Naifeng Jing (ISCAS, 2024)

RecPIM: Efficient In-Memory Processing for Personalized Recommendation Inference Using Near-Bank Architecture. - Weidong Yang; Yuqing Yang; Shuya Ji; Jianfei Jiang 001; Naifeng Jing; Qin Wang 009; Zhigang Mao; Weiguang Sheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

HEILP: An ILP-Based Scale Management Method for Homomorphic Encryption Compiler. - Weidong Yang; Shuya Ji; Jianfei Jiang 001; Naifeng Jing; Qin Wang 009; Zhigang Mao; Weiguang Sheng (DATE, 2025)

A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip. - Zizheng Dong; Shuaipeng Li; Weijia Zhu; Ang Li; Qin Wang 009; Naifeng Jing; Weiguang Sheng; Jianfei Jiang 001; Zhigang Mao (IEEE Trans. Very Large Scale Integr. Syst., 2025)

IPDR: An Inter-Chiplet Priority-Driven Deadlock Resolution for 2-D/2.5-D Multichiplet Systems. - Jinming Zhang; Zhihong Chen; Yaoyao Ye; Hao Chen; Xiao Han; Jianfei Jiang 001; Weiguang Sheng; Ningyi Xu; Yong Lian 001; Guanghui He (IEEE Trans. Very Large Scale Integr. Syst., 2025)