Efficient Circuit for Parallel Bit Reversal. - Weijun Li 001; Feng Yu 003; Zhen-guo Ma (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Modular Serial Pipelined Sorting Architecture for Continuous Variable-Length Sequences with a Very Simple Control Strategy. - Tingting Chen; Weijun Li 001; Feng Yu 003; Qianjian Xing (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Resource-Efficient Parallel Tree-Based Join Architecture on FPGA. - Huan Zhang 004; Bei Zhao; Wei-Jun Li 001; Zhen-Guo Ma; Feng Yu 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Sorting Matrix Architecture for Continuous Data Sequences. - Meiting Xue; Huan Zhang 004; Weijun Li 001; Feng Yu 003 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020)

A Hybrid Pipelined Architecture for High Performance Top-K Sorting on FPGA. - Weijie Chen 001; Weijun Li 001; Feng Yu 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Modular Pipeline Architecture for Accelerating Join Operation in RDBMS. - Weijie Chen 001; Weijun Li 001; Feng Yu 003 (IEEE Trans. Circuits Syst., 2020)