Multi-core architecture with asynchronous clocks to prevent power analysis attacks. - Yuan Du; Yong Ye; Weiliang Jing; Zhenhua Li; Xiaoyun Li; Zhitang Song; Bomy Chen (IEICE Electron. Express, 2017)

Logic area reduction using the deep trench isolation technique based on 40 nm embedded PCM process. - Yuan Du; Yong Ye; Weiliang Jing; Xiaoyun Li; Zhitang Song; Bomy Chen (IEICE Electron. Express, 2017)

CAM-based retention-aware DRAM (CRA-DRAM) for refresh power reduction. - Yong Ye; Yuan Du; Weiliang Jing; Xiaoyun Li; Zhitang Song; Bomy Chen (IEICE Electron. Express, 2017)

Erratum: CAM-based retention-aware DRAM (CRA-DRAM) for refresh power reduction [IEICE Electronics Express Vol. 14 (2017) No. 10 pp. 20170053]. - Yong Ye; Yuan Du; Weiliang Jing; Xiaoyun Li; Zhitang Song; Bomy Chen (IEICE Electron. Express, 2017)

Retention-Aware Hybrid Main Memory (RAHMM): Big DRAM and Little SCM. - Weiliang Jing; Kai Yang; Yinyin Lin; Beomseop Lee; Sangkyu Yoon; Yong Ye; Yuan Du; Bomy Chen (IEEE Trans. Computers, 2017)

Subsystem under 3D-Storage Class Memory on a chip. - Jipeng Guo 002; Haibo Wang; Weiliang Jing; Haixin Li; Yuan Du; Zhitang Song; Bomy Chen (Comput. Electr. Eng., 2019)

Compact Modeling of IGZO-based CAA-FETs with Time-zero-instability and BTI Impact on Device and Capacitor-less DRAM Retention Reliability. - Jingrui Guo; Ying Sun; Lingfei Wang; Xinlv Duan; Kailiang Huang; Zhaogui Wang; Junxiao Feng; Qian Chen; Shijie Huang; Lihua Xu; Di Geng; Guangfan Jiao; et al. (VLSI Technology and Circuits, 2022)

Vertical Channel-All-Around (CAA) IGZO FET under 50 nm CD with High Read Current of 32.8 μA/μm (Vth + 1 V), Well-performed Thermal Stability up to 120 ℃ for Low Latency, High-density 2T0C 3D DRAM Application. - Kailiang Huang; Xinlv Duan; Junxiao Feng; Ying Sun; Congyan Lu; Chuanke Chen; Guangfan Jiao; Xinpeng Lin; Jinhai Shao; Shihui Yin; Jiazhen Sheng; Zhaogui Wang; et al. (VLSI Technology and Circuits, 2022)