A 2-2 MASH ΔΣ ADC with fast-charge CLS input buffer and dual double sampling achieving 103.3-dB SNDR and ±2.5-ppm/FSR INL. - Yang Chen 046; Binyu Cai; Changhuan Chen; Weiliang Peng; Quan Sun; Xiaofei Wang; Hong Zhang 009 (Microelectron. J., 2024)

A 10-kHz BW 104.3-dB DR discrete-time delta-sigma modulator with ring-amplifier-based integrator. - Yuming Li; Shuai Peng; Weiliang Peng; Yang Chen 046; Zhiming Li; Jie Zhang 039; Xiaofei Wang; Hong Zhang 009 (Microelectron. J., 2024)