Functional Model of Carbon Nanotube Programmable Resistors for Hybrid Nano/CMOS Circuit Design. - Weisheng Zhao 001; Guillaume Agnus; Vincent Derycke; Arianna Filoramo; Christian Gamrat; Jean-Philippe Bourgoin (NanoNet, 2009)

High Density Asynchronous LUT Based on Non-volatile MRAM Technology. - Sumanta Chaudhuri; Weisheng Zhao 001; Jacques-Olivier Klein; Claude Chappert; Pascale Mazoyer (FPL, 2010)

Design of embedded MRAM macros for memory-in-logic applications. - Sumanta Chaudhuri; Weisheng Zhao 001; Jacques-Olivier Klein; Claude Chappert; Pascale Mazoyer (ACM Great Lakes Symposium on VLSI, 2010)

Carbon nanotube-based programmable devices for adaptive architectures. - Guillaume Agnus; Arianna Filoramo; Jean-Philippe Bourgoin; Vincent Derycke; Weisheng Zhao 001 (ISCAS, 2010)

Magnetic Look-Up Table (MLUT) Featuring Radiation Hardness, High Performance and Low Power. - Yahya Lakys; Weisheng Zhao 001; Jacques-Olivier Klein; Claude Chappert (ARC, 2011)

Design of MRAM based logic circuits and its applications. - Weisheng Zhao 001; Lionel Torres; Yoann Guillemenet; Luis Vitorio Cargnini; Yahya Lakys; Jacques-Olivier Klein; Dafine Ravelosona; Gilles Sassatelli; Claude Chappert (ACM Great Lakes Symposium on VLSI, 2011)

Robust neural logic block (NLB) based on memristor crossbar array. - Djaafar Chabi; Weisheng Zhao 001; Damien Querlioz; Jacques-Olivier Klein (NANOARCH, 2011)

High Performance SoC Design Using Magnetic Logic and Memory. - Weisheng Zhao 001; Lionel Torres; Luis Vitorio Cargnini; Raphael Martins Brum; Yue Zhang 010; Yoann Guillemenet; Gilles Sassatelli; Yahya Lakys; Jacques-Olivier Klein; Daniel Etiemble; Dafine Ravelosona; Claude Chappert (VLSI-SoC (Selected Papers), 2011)

Embedded MRAM for high-speed computing. - Weisheng Zhao 001; Yue Zhang 010; Yahya Lakys; Jacques-Olivier Klein; Daniel Etiemble; D. Revelosona; Claude Chappert; Lionel Torres; Luis Vitorio Cargnini; Raphael Martins Brum; Yoann Guillemenet; Gilles Sassatelli (VLSI-SoC, 2011)

Design considerations and strategies for high-reliable STT-MRAM. - Weisheng Zhao 001; Thibaut Devolder; Yahya Lakys; Jacques-Olivier Klein; Claude Chappert; Pascale Mazoyer (Microelectron. Reliab., 2011)

Design and Modeling of a Neuro-Inspired Learning Circuit Using Nanotube-Based Memory Devices. - Si-Yu Liao; Jean-Marie Retrouvey; Guillaume Agnus; Weisheng Zhao 001; Cristell Maneux; Sébastien Fregonese; Thomas Zimmer; Djaafar Chabi; Arianna Filoramo; Vincent Derycke; Christian Gamrat; Jacques-Olivier Klein (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

MRAM crossbar based configurable logic block. - Yahya Lakys; Weisheng Zhao 001; Jacques-Olivier Klein; Claude Chappert (ISCAS, 2012)

Nanodevice-based novel computing paradigms and the neuromorphic approach. - Weisheng Zhao 001; Damien Querlioz; Jacques-Olivier Klein; Djaafar Chabi; Claude Chappert (ISCAS, 2012)

Bioinspired networks with nanoscale memristive devices that combine the unsupervised and supervised learning approaches. - Damien Querlioz; Weisheng Zhao 001; Philippe Dollfus; Jacques-Olivier Klein; Olivier Bichler; Christian Gamrat (NANOARCH, 2012)

Crossbar architecture based on 2R complementary resistive switching memory cell. - Weisheng Zhao 001; Yue Zhang 010; Jacques-Olivier Klein; Damien Querlioz; Djaafar Chabi; Dafine Ravelosona; Claude Chappert; Jean-Michel Portal; Marc Bocquet; Hassen Aziza; Damien Deleruyelle; Christophe Muller (NANOARCH, 2012)

Cross-point architecture for spin transfer torque magnetic random access memory - Weisheng Zhao 001; Sumanta Chaudhuri; Celso Accoto; Jacques-Olivier Klein; Claude Chappert; Pascale Mazoyer (CoRR, 2012)

Failure and reliability analysis of STT-MRAM. - Weisheng Zhao 001; Yue Zhang 010; Thibaut Devolder; Jacques-Olivier Klein; Dafine Ravelosona; Claude Chappert; Pascale Mazoyer (Microelectron. Reliab., 2012)

Analytical study of complementary memristive synchronous logic gates. - Jean-Michel Portal; Mathieu Moreau; Marc Bocquet; Hassen Aziza; Damien Deleruyelle; Christophe Muller; Yue Zhang 010; Erya Deng; Jacques-Olivier Klein; Damien Querlioz; Dafine Ravelosona; Claude Chappert; et al. (NANOARCH, 2013)

Low power magnetic flip-flop based on checkpointing and self-enable mechanism. - Djaafar Chabi; Weisheng Zhao 001; Yue Zhang 010; Jacques-Olivier Klein; Claude Chappert (NEWCAS, 2013)

Synchronous full-adder based on complementary resistive switching memory cells. - Yue Zhang 010; Erya Deng; Jacques-Olivier Klein; Damien Querlioz; Dafine Ravelosona; Claude Chappert; Weisheng Zhao 001; Mathieu Moreau; Jean-Michel Portal; Marc Bocquet; Hassen Aziza; Damien Deleruyelle; et al. (NEWCAS, 2013)

Emerging hybrid logic circuits based on non-volatile magnetic memories. - Weisheng Zhao 001; Guillaume Prenat; Jacques-Olivier Klein; Bernard Dieny; Claude Chappert; Dafine Ravelosona (NEWCAS, 2013)

Spin-electronics based logic fabrics. - Weisheng Zhao 001; Jacques-Olivier Klein; Zhaohao Wang; Yue Zhang 010; Nesrine Ben Romdhane; Damien Querlioz; Dafine Ravelosona; Claude Chappert (VLSI-SoC, 2013)

A low-cost built-in error correction circuit design for STT-MRAM reliability improvement. - Wang Kang 001; Weisheng Zhao 001; Zhaohao Wang; Yue Zhang 010; Jacques-Olivier Klein; Youguang Zhang; Claude Chappert; Dafine Ravelosona (Microelectron. Reliab., 2013)

Magnetic Adder Based on Racetrack Memory. - Hong-Phuc Trinh; Weisheng Zhao 001; Jacques-Olivier Klein; Yue Zhang 010; Dafine Ravelosona; Claude Chappert (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

An overview of spin-based integrated circuits. - Wang Kang 001; Weisheng Zhao 001; Zhaohao Wang; Jacques-Olivier Klein; Yue Zhang 010; Djaafar Chabi; Youguang Zhang; Dafine Ravelosona; Claude Chappert (ASP-DAC, 2014)

Spintronics for low-power computing. - Yue Zhang 010; Weisheng Zhao 001; Jacques-Olivier Klein; Wang Kang 001; Damien Querlioz; Youguang Zhang; Dafine Ravelosona; Claude Chappert (DATE, 2014)

Ferroelectric tunnel memristor-based neuromorphic network with 1T1R crossbar architecture. - Zhaohao Wang; Weisheng Zhao 001; Wang Kang 001; Youguang Zhang; Jacques-Olivier Klein; Claude Chappert (IJCNN, 2014)

Spin-transfer torque magnetic memory as a stochastic memristive synapse. - Adrien F. Vincent; Jerome Larroque; Weisheng Zhao 001; Nesrine Ben Romdhane; Olivier Bichler; Christian Gamrat; Jacques-Olivier Klein; Sylvie Galdin-Retailleau; Damien Querlioz (ISCAS, 2014)

On-chip supervised learning rule for ultra high density neural crossbar using memristor for synapse and neuron. - Djaafar Chabi; Zhaohao Wang; Weisheng Zhao 001; Jacques-Olivier Klein (NANOARCH, 2014)

Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowires. - Nesrine Ben Romdhane; Weisheng Zhao 001; Yue Zhang 010; Jacques-Olivier Klein; Z. R. Wang; Dafine Ravelosona (NANOARCH, 2014)

One-step majority-logic-decodable codes enable STT-MRAM for high speed working memories. - Wang Kang 001; Weisheng Zhao 001; Lun Yang; Jacques-Olivier Klein; Youguang Zhang; Dafine Ravelosona (NVMSA, 2014)

Robust learning approach for neuro-inspired nanoscale crossbar architecture. - Djaafar Chabi; Damien Querlioz; Weisheng Zhao 001; Jacques-Olivier Klein (ACM J. Emerg. Technol. Comput. Syst., 2014)

Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells. - Weisheng Zhao 001; Jean-Michel Portal; Wang Kang 001; Mathieu Moreau; Yue Zhang 010; Hassen Aziza; Jacques-Olivier Klein; Zhaohao Wang; Damien Querlioz; Damien Deleruyelle; Marc Bocquet; Dafine Ravelosona; et al. (J. Parallel Distributed Comput., 2014)

Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses. - You Wang 002; Yue Zhang 010; Erya Deng; Jacques-Olivier Klein; Lirida A. B. Naviner; Weisheng Zhao 001 (Microelectron. Reliab., 2014)

Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms. - Djaafar Chabi; Weisheng Zhao 001; Erya Deng; Yue Zhang 010; Nesrine Ben Romdhane; Jacques-Olivier Klein; Claude Chappert (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories. - Weisheng Zhao 001; Mathieu Moreau; Erya Deng; Yue Zhang 010; Jean-Michel Portal; Jacques-Olivier Klein; Marc Bocquet; Hassen Aziza; Damien Deleruyelle; Christophe Muller; Damien Querlioz; Nesrine Ben Romdhane; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Spin orbit torques for ultra-low power computing. - Kaihua Cao; Heng Zhao; Mengxing Wang 001; Weisheng Zhao 001 (ASICON, 2015)

Recent progresses of STT memory design and applications. - Bonan Yan; Yaojun Zhang; Enes Eken; Wujie Wen; Weisheng Zhao 001; Yiran Chen 001 (ASICON, 2015)

Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power. - Chao Zhang 007; Guangyu Sun 003; Weiqi Zhang; Fan Mi; Hai Li 001; Weisheng Zhao 001 (ASP-DAC, 2015)

Spintronic devices as key elements for energy-efficient neuroinspired architectures. - Nicolas Locatelli; Adrien F. Vincent; Alice Mizrahi; Joseph S. Friedman; Damir Vodenicarevic; Joo-Von Kim; Jacques-Olivier Klein; Weisheng Zhao 001; Julie Grollier; Damien Querlioz (DATE, 2015)

From device to system: cross-layer design exploration of racetrack memory. - Guangyu Sun 003; Chao Zhang 007; Hehe Li; Yue Zhang 010; Weiqi Zhang; Yizi Gu; Yinan Sun; Jacques-Olivier Klein; Dafine Ravelosona; Yongpan Liu; Weisheng Zhao 001; Huazhong Yang (DATE, 2015)

A High-Speed Robust NVM-TCAM Design Using Body Bias Feedback. - Bonan Yan; Zheng Li; Yaojun Zhang; Jianlei Yang 001; Hai Li 001; Weisheng Zhao 001; Pierre Chor-Fung Chia (ACM Great Lakes Symposium on VLSI, 2015)

Hi-fi playback: tolerating position errors in shift operations of racetrack memory. - Chao Zhang 007; Guangyu Sun 003; Xian Zhang 001; Weiqi Zhang; Weisheng Zhao 001; Tao Wang 004; Yun Liang 001; Yongpan Liu; Yu Wang 002; Jiwu Shu (ISCA, 2015)

A new self-reference sensing scheme for TLC MRAM. - Zheng Li; Bonan Yan; Lun Yang; Weisheng Zhao 001; Yiran Chen 001; Hai Li 001 (ISCAS, 2015)

Vortex-based spin transfer oscillator compact model for IC design. - Nicolas Locatelli; Damir Vodenicarevic; Weisheng Zhao 001; Jacques-Olivier Klein; Julie Grollier; Damien Querlioz (ISCAS, 2015)

A body-biasing of readout circuit for STT-RAM with improved thermal reliability. - Lun Yang; Yuanqing Cheng; Yuhao Wang 002; Hao Yu 001; Weisheng Zhao 001; Aida Todri-Sanial (ISCAS, 2015)

Perspectives of racetrack memory based on current-induced domain wall motion: From device to system. - Yue Zhang 010; Chao Zhang 007; Jacques-Olivier Klein; Dafine Ravelosona; Guangyu Sun 003; Weisheng Zhao 001 (ISCAS, 2015)

Energy-efficient neuromorphic computation based on compound spin synapse with stochastic learning. - Deming Zhang; Lang Zeng; Yuanzhuo Qu; Youguang Zhang; Mengxing Wang 001; Weisheng Zhao 001; Tianqi Tang 001; Yu Wang 002 (ISCAS, 2015)

Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM. - Liuyang Zhang; Wang Kang 001; Youguang Zhang; Yuanqing Cheng; Lang Zeng; Jacques-Olivier Klein; Weisheng Zhao 001 (ISVLSI, 2015)

Full-adder circuit design based on all-spin logic device. - Qi An; Li Su; Jacques-Olivier Klein; Sébastien Le Beux; Ian O'Connor; Weisheng Zhao 001 (NANOARCH, 2015)

Robust magnetic full-adder with voltage sensing 2T/2MTJ cell. - Erya Deng; You Wang 002; Zhaohao Wang; Jacques-Olivier Klein; Bernard Dieny; Guillaume Prenat; Weisheng Zhao 001 (NANOARCH, 2015)

An architecture-level cache simulation framework supporting advanced PMA STT-MRAM. - Bi Wu 002; Yuanqing Cheng; Ying Wang 001; Aida Todri-Sanial; Guangyu Sun 003; Lionel Torres; Weisheng Zhao 001 (NANOARCH, 2015)

Stochastic computation with Spin Torque Transfer Magnetic Tunnel Junction. - Lirida Alves de Barros Naviner; Hao Cai 001; You Wang 002; Weisheng Zhao 001; Arwa Ben Dhia (NEWCAS, 2015)

Read disturbance issue for nanoscale STT-MRAM. - Yi Ran; Wang Kang 001; Youguang Zhang; Jacques-Olivier Klein; Weisheng Zhao 001 (NVMSA, 2015)

Nonvolatile radiation hardened DICE latch. - Tingting Pang; Wang Kang 001; Yi Ran; Youguang Zhang; Weifeng Lv; Weisheng Zhao 001 (NVMTS, 2015)

Realization of neural coding by stochastic switching of magnetic tunnel junction. - Deming Zhang; Lang Zeng; Fanghui Gong; Tianqi Gao; Shaolong Gao; Youguang Zhang; Weisheng Zhao 001 (NVMTS, 2015)

Yield and Reliability Improvement Techniques for Emerging Nonvolatile STT-MRAM. - Wang Kang 001; Liuyang Zhang; Weisheng Zhao 001; Jacques-Olivier Klein; Youguang Zhang; Dafine Ravelosona; Claude Chappert (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

On-Chip Universal Supervised Learning Methods for Neuro-Inspired Block of Memristive Nanodevices. - Djaafar Chabi; Weisheng Zhao 001; Damien Querlioz; Jacques-Olivier Klein (ACM J. Emerg. Technol. Comput. Syst., 2015)

Spintronics: Emerging Ultra-Low-Power Circuits and Systems beyond MOS Technology. - Wang Kang 001; Yue Zhang 010; Zhaohao Wang; Jacques-Olivier Klein; Claude Chappert; Dafine Ravelosona; Gefei Wang; Youguang Zhang; Weisheng Zhao 001 (ACM J. Emerg. Technol. Comput. Syst., 2015)

Tunnel Junction with Perpendicular Magnetic Anisotropy: Status and Challenges. - Mengxing Wang 001; Yue Zhang 010; Xiaoxuan Zhao; Weisheng Zhao 001 (Micromachines, 2015)

Compact thermal modeling of spin transfer torque magnetic tunnel junction. - You Wang 002; Hao Cai 001; Lirida A. B. Naviner; Yue Zhang 010; Jacques-Olivier Klein; Weisheng Zhao 001 (Microelectron. Reliab., 2015)

Spin-Transfer Torque Magnetic Memory as a Stochastic Memristive Synapse for Neuromorphic Systems. - Adrien F. Vincent; Jerome Larroque; Nicolas Locatelli; Nesrine Ben Romdhane; Olivier Bichler; Christian Gamrat; Weisheng Zhao 001; Jacques-Olivier Klein; Sylvie Galdin-Retailleau; Damien Querlioz (IEEE Trans. Biomed. Circuits Syst., 2015)

Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction. - Erya Deng; Yue Zhang 010; Wang Kang 001; Bernard Dieny; Jacques-Olivier Klein; Guillaume Prenat; Weisheng Zhao 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Guest Editorial for Special Issue on Emerging Memory Technologies - Modeling, Design, and Applications for Multi-Scale Computing. - Yiran Chen 001; Kiyoung Choi; Weisheng Zhao 001 (IEEE Trans. Multi Scale Comput. Syst., 2015)

PDS: pseudo-differential sensing scheme for STT-MRAM. - Wang Kang 001; Tingting Pang; Bi Wu 002; Weifeng Lv; Youguang Zhang; Guangyu Sun 003; Weisheng Zhao 001 (DAC, 2016)

Spin wave based synapse and neuron for ultra low power neuromorphic computation system. - Lang Zeng; Deming Zhang; Youguang Zhang; Fanghui Gong; Tianqi Gao; Sa Tu; Haiming Yu; Weisheng Zhao 001 (ISCAS, 2016)

Quantitative evaluation of reliability and performance for STT-MRAM. - Liuyang Zhang; Aida Todri-Sanial; Wang Kang 001; Youguang Zhang; Lionel Torres; Yuanqing Cheng; Weisheng Zhao 001 (ISCAS, 2016)

Approximate computing in MOS/spintronic non-volatile full-adder. - Hao Cai 001; You Wang 002; Lirida A. B. Naviner; Zhaohao Wang; Weisheng Zhao 001 (NANOARCH, 2016)

Evaluation of spin-Hall-assisted STT-MRAM for cache replacement. - Liang Chang 002; Zhaohao Wang; Yuqian Gao; Wang Kang 001; Youguang Zhang; Weisheng Zhao 001 (NANOARCH, 2016)

A spin Hall effect-based multi-level cell for MRAM. - Qian Shi; Zhaohao Wang; Yuqian Gao; Liang Chang 002; Wang Kang 001; Youguang Zhang; Weisheng Zhao 001 (NANOARCH, 2016)

A novel circuit design of true random number generator using magnetic tunnel junction. - You Wang 002; Hao Cai 001; Lirida A. B. Naviner; Jacques-Olivier Klein; Jianlei Yang 001; Weisheng Zhao 001 (NANOARCH, 2016)

Dual reference sensing scheme with triple steady states for deeply scaled STT-MRAM. - He Zhang 011; Wang Kang 001; Tingting Pang; Weifeng Lv; Youguang Zhang; Weisheng Zhao 001 (NANOARCH, 2016)

Ultra-low power all spin logic device acceleration based on voltage controlled magnetic anisotropy. - Zhizhong Zhang 004; Yue Zhang 010; Lei Yue; Li Su; Yichuan Shi; Youguang Zhang; Weisheng Zhao 001 (NANOARCH, 2016)

Stochastic spintronic device based synapses and spiking neurons for neuromorphic computation. - Deming Zhang; Lang Zeng; Youguang Zhang; Weisheng Zhao 001; Jacques-Olivier Klein (NANOARCH, 2016)

Magnetic skyrmion-based synaptic devices. - Yangqi Huang; Wang Kang 001; Xichao Zhang; Yan Zhou; Weisheng Zhao 001 (CoRR, 2016)

Skyrmions as Compact, Robust and Energy-Efficient Interconnects for Domain Wall (DW)-based Systems. - Wang Kang 001; Yangqi Huang; Xichao Zhang; Yan Zhou; Weifeng Lv; Weisheng Zhao 001 (CoRR, 2016)

Complementary Skyrmion Racetrack Memory with Voltage Manipulation. - Wang Kang 001; Chentian Zheng; Yangqi Huang; Xichao Zhang; Yan Zhou; Weifeng Lv; Weisheng Zhao 001 (CoRR, 2016)

Read disturbance issue and design techniques for nanoscale STT-MRAM. - Yi Ran; Wang Kang 001; Youguang Zhang; Jacques-Olivier Klein; Weisheng Zhao 001 (J. Syst. Archit., 2016)

A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI. - You Wang 002; Hao Cai 001; Lirida A. B. Naviner; Xiaoxuan Zhao; Yue Zhang 010; Mariem Slimani; Jacques-Olivier Klein; Weisheng Zhao 001 (Microelectron. Reliab., 2016)

Skyrmion-Electronics: An Overview and Outlook. - Wang Kang 001; Yangqi Huang; Xichao Zhang; Yan Zhou; Weisheng Zhao 001 (Proc. IEEE, 2016)

All Spin Artificial Neural Networks Based on Compound Spintronic Synapse and Neuron. - Deming Zhang; Lang Zeng; Kaihua Cao; Mengxing Wang 001; Shouzhong Peng; Yue Zhang 010; Youguang Zhang; Jacques-Olivier Klein; Yu Wang 002; Weisheng Zhao 001 (IEEE Trans. Biomed. Circuits Syst., 2016)

Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach. - Jianlei Yang 001; Peiyuan Wang; Yaojun Zhang; Yuanqing Cheng; Weisheng Zhao 001; Yiran Chen 001; Hai (Helen) Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System. - Yue Zhang 010; Chao Zhang 007; Jiang Nan; Zhizhong Zhang 004; Xueying Zhang; Jacques-Olivier Klein; Dafine Ravelosona; Guangyu Sun 003; Weisheng Zhao 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM. - Bi Wu 002; Yuanqing Cheng; Jianlei Yang 001; Aida Todri-Sanial; Weisheng Zhao 001 (IEEE Trans. Reliab., 2016)

Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing Effect. - Yuanqing Cheng; Aida Todri-Sanial; Jianlei Yang 001; Weisheng Zhao 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Ultrafast spintronic integrated circuits. - Jiaqi Wei; Liang Chang 002; Zhaohao Wang; Xiaoyang Lin; Kaihua Cao; Hushan Cui; Wang Kang 001; Haoxuan Chen; Lang Zeng; Youguang Zhang; Chao Zhao; Weisheng Zhao 001 (ASICON, 2017)

Voltage-controlled MRAM for working memory: Perspectives and challenges. - Wang Kang 001; Liang Chang 002; Youguang Zhang; Weisheng Zhao 001 (DATE, 2017)

A true random number generator based on parallel STT-MTJs. - Yuanzhuo Qu; Jie Han 001; Bruce F. Cockburn; Witold Pedrycz; Yue Zhang 010; Weisheng Zhao 001 (DATE, 2017)

Energy Efficient Magnetic Tunnel Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI Device. - Hao Cai 001; You Wang 002; Lirida A. B. Naviner; Wang Kang 001; Weisheng Zhao 001 (ACM Great Lakes Symposium on VLSI, 2017)

Advanced Low Power Spintronic Memories beyond STT-MRAM. - Wang Kang 001; Zhaohao Wang; He Zhang 011; Sai Li; Youguang Zhang; Weisheng Zhao 001 (ACM Great Lakes Symposium on VLSI, 2017)

PRESCOTT: Preset-based cross-point architecture for spin-orbit-torque magnetic random access memory. - Liang Chang 002; Zhaohao Wang; Alvin Oliver Glova; Jishen Zhao; Youguang Zhang; Yuan Xie 001; Weisheng Zhao 001 (ICCAD, 2017)

Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs. - Bi Wu 002; Yuanqing Cheng; Pengcheng Dai; Jianlei Yang 001; Youguang Zhang; Dijun Liu; Ying Wang 001; Weisheng Zhao 001 (ICCAD, 2017)

Programmable Stateful In-Memory Computing Paradigm via a Single Resistive Device. - Wang Kang 001; He Zhang 011; Peng Ouyang; Youguang Zhang; Weisheng Zhao 001 (ICCD, 2017)

Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core. - Hao Cai 001; You Wang 002; Lirida A. B. Naviner; Weisheng Zhao 001 (ISVLSI, 2017)

Reconfigurable processing in memory architecture based on spin orbit torque. - Liang Chang 002; Zhaohao Wang; Youguang Zhang; Weisheng Zhao 001 (NANOARCH, 2017)

Proposal for novel magnetic memory device with spin momentum locking materials. - Xiaowan Qin; Lang Zeng; Tianqi Gao; Deming Zhang; Mingzhi Long; Youguang Zhang; Weisheng Zhao 001 (NANOARCH, 2017)

Compact modeling of high spin transfer torque efficiency double-barrier magnetic tunnel junction. - Guanda Wang; Yue Zhang 010; Zhizhong Zhang 004; Jiang Nan; Zhenyi Zheng; Yu Wang 172; Lang Zeng; Youguang Zhang; Weisheng Zhao 001 (NANOARCH, 2017)

Frequency modulation of spin torque nano oscillator with voltage controlled magnetic anisotropy effect. - Zuodong Zhang; Lang Zeng; Tianqi Gao; Deming Zhang; Xiaowan Qin; Mingzhi Long; Youguang Zhang; Haiming Yu; Weisheng Zhao 001 (NANOARCH, 2017)

Arithmetic Logic Unit based on all-spin logic devices. - Qi An; Sébastien Le Beux; Ian O'Connor; Jacques-Olivier Klein; Weisheng Zhao 001 (NEWCAS, 2017)

Interfacial property tuning of heavy metal/CoFeB for large density STT-MRAM. - Wenlong Cai; Kaihua Cao; Mengxing Wang 001; Shouzhong Peng; Jiaqi Zhou 002; Anni Cao; Boyu Zhang; Lezhi Wang; Yu Zhang; Jiaqi Wei; Xiaobin He; Hushan Cui; et al. (NVMTS, 2017)

Pseudo-Differential Sensing Framework for STT-MRAM: A Cross-Layer Perspective. - Wang Kang 001; Liang Chang 002; Zhaohao Wang; Weifeng Lv; Guangyu Sun 003; Weisheng Zhao 001 (IEEE Trans. Computers, 2017)

Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology. - Hao Cai 001; You Wang 002; Lirida Alves de Barros Naviner; Weisheng Zhao 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Dynamic Dual-Reference Sensing Scheme for Deep Submicrometer STT-MRAM. - Wang Kang 001; Tingting Pang; Weifeng Lv; Weisheng Zhao 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Stability and Variability Emphasized STT-MRAM Sensing Circuit With Performance Enhancement. - Menglin Han; Hao Cai 001; Jun Yang 006; Lirida A. B. Naviner; You Wang 002; Weisheng Zhao 001 (APCCAS, 2018)

A Novel 15T-4MTJ based Non-volatile Ternary Content-Addressable Memory Cell for High-Speed, Low-Power and High-Reliable Search Operation. - Chengzhi Wang; Deming Zhang; Lang Zeng; Jie Chen 009; Weisheng Zhao 001 (APCCAS, 2018)

High-Density and Fast-Configuration Non-Volatile Look-Up Table Based on NAND-Like Spintronic Memory. - He Zhang 011; Wang Kang 001; Zhaohao Wang; Erya Deng; Youguang Zhang; Weisheng Zhao 001 (APCCAS, 2018)

Process variation aware data management for magnetic skyrmions racetrack memory. - Fan Chen 001; Zheng Li; Wang Kang 001; Weisheng Zhao 001; Hai Li 001; Yiran Chen 001 (ASP-DAC, 2018)

Spintronics based stochastic computing for efficient Bayesian inference system. - Xiaotao Jia; Jianlei Yang 001; Zhaohao Wang; Yiran Chen 001; Hai Helen Li; Weisheng Zhao 001 (ASP-DAC, 2018)

Magnetic skyrmions for future potential memory and logic applications: Alternative information carriers. - Wang Kang 001; Xing Chen 012; Daoqian Zhu; Sai Li; Yangqi Huang; Youguang Zhang; Weisheng Zhao 001 (DATE, 2018)

Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power. - Hao Cai 001; Menglin Han; You Wang 002; Lirida A. B. Naviner; Xinning Liu; Jun Yang 006; Weisheng Zhao 001 (DCIS, 2018)

A Scalable Pipelined Dataflow Accelerator for Object Region Proposals on FPGA Platform. - Wenzhi Fu; Jianlei Yang 001; Pengcheng Dai; Yiran Chen 001; Weisheng Zhao 001 (FPT, 2018)

Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep Learning. - You Wang 002; Yue Zhang 010; Youguang Zhang; Weisheng Zhao 001; Hao Cai 001; Lirida A. B. Naviner (ACM Great Lakes Symposium on VLSI, 2018)

Enabling Resilient Voltage-Controlled MeRAM Using Write Assist Techniques. - Hao Cai 001; You Wang 002; Wang Kang 001; Lirida A. B. Naviner; Weiwei Shan; Jun Yang 006; Weisheng Zhao 001 (ISCAS, 2018)

Design and Data Management for Magnetic Racetrack Memory. - Bing Li 017; Fan Chen 001; Wang Kang 001; Weisheng Zhao 001; Yiran Chen 001; Hai Li 001 (ISCAS, 2018)

NEAR: A Novel Energy Aware Replacement Policy for STT-MRAM LLCs. - Chen Liu; Yuanqing Cheng; Ying Wang 001; Youguang Zhang; Weisheng Zhao 001 (ISCAS, 2018)

Progresses and challenges of spin orbit torque driven magnetization switching and application (Invited). - Zhaohao Wang; Zuwei Li; Yang Liu; Simin Li; Liang Chang 002; Wang Kang 001; Youguang Zhang; Weisheng Zhao 001 (ISCAS, 2018)

Radiation hardening design for spin-orbit torque magnetic random access memory. - Bi Wang 002; Zhaohao Wang; Kaihua Cao; Youguang Zhang; Yuanfu Zhao; Weisheng Zhao 001 (ISCAS, 2018)

MRAM-on-FDSOI Integration: A Bit-Cell Perspective. - Hao Cai 001; You Wang 002; Wang Kang 001; Lirida A. B. Naviner; Xinning Liu; Jun Yang 006; Weisheng Zhao 001 (ISVLSI, 2018)

Emerging Neuromorphic Computing Paradigms Exploring Magnetic Skyrmions. - Sai Li; Wang Kang 001; Xing Chen 012; Jinyu Bai; Biao Pan; Youguang Zhang; Weisheng Zhao 001 (ISVLSI, 2018)

Write Energy Optimization for STT-MRAM Cache with Data Pattern Characterization. - Bi Wu 002; Xiaolong Zhang; Yuanqing Cheng; Zhaohao Wang; Dijun Liu; Youguang Zhang; Weisheng Zhao 001 (ISVLSI, 2018)

A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAM. - Liuyang Zhang; Wang Kang 001; Hao Cai 001; Peng Ouyang; Lionel Torres; Youguang Zhang; Aida Todri-Sanial; Weisheng Zhao 001 (ISVLSI, 2018)

A Novel Cross-point MRAM with Diode Selector Capable of High-Density, High-Speed, and Low-Power In-Memory Computation. - Chaoxin Ding; Wang Kang 001; He Zhang 011; Youguang Zhang; Weisheng Zhao 001 (NANOARCH, 2018)

Hardware Acceleration Implementation of Sparse Coding Algorithm with Spintronic Devices. - Deming Zhang; Yanchun Hou; Chengzhi Wang; Jie Chen 009; Lang Zeng; Weisheng Zhao 001 (NANOARCH, 2018)

A Comparative Study on Racetrack Memories: Domain Wall vs. Skyrmion. - Wang Kang 001; Xing Chen 012; Daoqian Zhu; Xichao Zhang; Yan Zhou; Keni Qiu; Youguang Zhang; Weisheng Zhao 001 (NVMSA, 2018)

Multi-bit nonvolatile flip-flop based on NAND-like spin transfer torque MRAM. - Erya Deng; Zhaohao Wang; Wang Kang 001; Shaoqian Wei; Weisheng Zhao 001 (VLSI-SoC, 2018)

A Full-Sensing-Margin Dual-Reference Sensing Scheme for Deeply-Scaled STT-RAM. - He Zhang 011; Wang Kang 001; Youguang Zhang; Meng-Fan Chang; Weisheng Zhao 001 (IEEE Access, 2018)

Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint. - Yinglin Zhao; Jianlei Yang 001; Weisheng Zhao 001; Aida Todri-Sanial; Yuanqing Cheng (J. Comput. Sci. Technol., 2018)

A Fast and Power-Efficient Hardware Architecture for Visual Feature Detection in Affine-SIFT. - Peng Ouyang; Shouyi Yin; Leibo Liu; Youguang Zhang; Weisheng Zhao 001; Shaojun Wei (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Ultra-low power consumption Spintronics Devices. - Zongxia Guo; Kaihua Cao; Kewen Shi; Weisheng Zhao 001 (ASICON, 2019)

ZUMA: Enabling Direct Insertion/Deletion Operations with Emerging Skyrmion Racetrack Memory. - Zheng Liang 003; Guangyu Sun 003; Wang Kang 001; Xing Chen 012; Weisheng Zhao 001 (DAC, 2019)

eSLAM: An Energy-Efficient Accelerator for Real-Time ORB-SLAM on FPGA Platform. - Runze Liu 001; Jianlei Yang 001; Yiran Chen 001; Weisheng Zhao 001 (DAC, 2019)

CORN: In-Buffer Computing for Binary Neural Network. - Liang Chang 002; Xin Ma; Zhaohao Wang; Youguang Zhang; Weisheng Zhao 001; Yuan Xie 001 (DATE, 2019)

Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOI. - Hao Cai 001; Menglin Han; Weiwei Shan; Jun Yang 006; You Wang 002; Wang Kang 001; Weisheng Zhao 001 (ACM Great Lakes Symposium on VLSI, 2019)

A Skyrmion Racetrack Memory based Computing In-memory Architecture for Binary Neural Convolutional Network. - Yu Pan; Peng Ouyang; Yinglin Zhao; Shouyi Yin; Youguang Zhang; Shaojun Wei; Weisheng Zhao 001 (ACM Great Lakes Symposium on VLSI, 2019)

Magnetic Skyrmion-Based Neural Recording System Design for Brain Machine Interface. - Biao Pan; Kang Wang 001; Xing Chen 012; Jinyu Bai; Jianlei Yang 001; Sai Li; Youguang Zhang; Weisheng Zhao 001 (ISCAS, 2019)

SR-WTA: Skyrmion Racing Winner-Takes-All Module for Spiking Neural Computing. - Biao Pan; Kang Wang 001; Xing Chen 012; Jinyu Bai; Jianlei Yang 001; Youguang Zhang; Weisheng Zhao 001 (ISCAS, 2019)

Modulation and Demodulation of Digital Frequency Shift Keying System Based on Spin Torque Nano Oscillator with Voltage Controlled Magnetic Anisotropy Effect. - Lang Zeng; Zuodong Zhang; Haoxuan Chen; Tianqi Gao; Deming Zhang; Mingzhi Long; Youguang Zhang; Weisheng Zhao 001 (ISCAS, 2019)

Ultra-fast and Energy-efficient Write-Computing Operation for Neuromorphic Computing. - Liang Chang 002; Zhaohao Wang; Youguang Zhang; Weisheng Zhao 001 (ISOCC, 2019)

Pj-AxMTJ: Process-in-memory with Joint Magnetization Switching for Approximate Computing in Magnetic Tunnel Junction. - Hao Cai 001; Honglan Jiang; Menglin Han; Zhaohao Wang; You Wang 002; Jun Yang 006; Jie Han 001; Leibo Liu; Weisheng Zhao 001 (ISVLSI, 2019)

Exploiting Near-Memory Processing Architectures for Bayesian Neural Networks Acceleration. - Yinglin Zhao; Jianlei Yang 001; Xiaotao Jia; Xueyan Wang; Zhaohao Wang; Wang Kang 001; Youguang Zhang; Weisheng Zhao 001 (ISVLSI, 2019)

Shaped Content Addressable Memory Based On Spin Orbit Torque Driven Chiral Domain Wall Motions. - Yue Zhang 010; Jiang Nan; Guanda Wang; Xueying Zhang; Youguang Zhang; Weisheng Zhao 001 (NANOARCH, 2019)

Process Variation-Resilient STT-MTJ based TRNG using Linear Correcting Codes. - Rashid Ali; You Wang 002; Zhengyi Hou; Haoyuan Ma; Youguang Zhang; Weisheng Zhao 001 (NANOARCH, 2019)

Spintronic Memories: From Memory to Computing-in-Memory. - Wang Kang 001; He Zhang 011; Weisheng Zhao 001 (NANOARCH, 2019)

Thermal Stable and Fast Perpendicular Shape Anisotropy Magnetic Tunnel Junction. - Guanda Wang; Yue Zhang 010; Zhe Huang; Jinkai Wang; Kun Zhang 030; Zhizhong Zhang 004; Youguang Zhang; Weisheng Zhao 001 (NANOARCH, 2019)

High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM. - Jinkai Wang; Yue Zhang 010; Chenyu Lian; Guanda Wang; Kun Zhang 030; Xiulong Wu; Youguang Zhang; Weisheng Zhao 001 (NANOARCH, 2019)

Low-Power, High-Speed and High-Density Magnetic Non-Volatile SRAM Design with Voltage-Gated Spin-Orbit Torque. - Chengzhi Wang; Deming Zhang; Lang Zeng; Kaili Zhang; Youguang Zhang; Weisheng Zhao 001 (NANOARCH, 2019)

Low-Power (1T1N) Skyrmionic Synapses for Spiking Neuromorphic Systems. - Tinish Bhattacharya; Sai Li; Yangqi Huang; Wang Kang 001; Weisheng Zhao 001; Manan Suri (IEEE Access, 2019)

Multi-Port 1R1W Transpose Magnetic Random Access Memory by Hierarchical Bit-Line Switching. - Liang Chang 002; Zhaohao Wang; Youguang Zhang; Weisheng Zhao 001 (IEEE Access, 2019)

Accelerating CNN Training by Sparsifying Activation Gradients. - Xucheng Ye; Jianlei Yang 001; Pengcheng Dai; Yiran Chen 001; Weisheng Zhao 001 (CoRR, 2019)

Erase-hidden and Drivability-improved Magnetic Non-Volatile Flip-Flops with NAND-SPIN Devices. - Ziyi Wang; Zhaohao Wang; Yansong Xu; Bi Wu 002; Weisheng Zhao 001 (CoRR, 2019)

An STT-MRAM Based in Memory Architecture for Low Power Integral Computing. - Yinglin Zhao; Peng Ouyang; Wang Kang 001; Shouyi Yin; Youguang Zhang; Shaojun Wei; Weisheng Zhao 001 (IEEE Trans. Computers, 2019)

Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit Obfuscation. - Jianlei Yang 001; Xueyan Wang; Qiang Zhou 001; Zhaohao Wang; Hai Li 001; Yiran Chen 001; Weisheng Zhao 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration. - Hao Cai 001; You Wang 002; Lirida Alves de Barros Naviner; Xinning Liu; Weiwei Shan; Jun Yang 006; Weisheng Zhao 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Novel Radiation Hardening Read/Write Circuits Using Feedback Connections for Spin-Orbit Torque Magnetic Random Access Memory. - Bi Wang 002; Zhaohao Wang; Bi Wu 002; Yumeng Bai; Kaihua Cao; Yuanfu Zhao; Youguang Zhang; Weisheng Zhao 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Novel MTJ-Based Non-Volatile Ternary Content-Addressable Memory for High-Speed, Low-Power, and High-Reliable Search Operation. - Chengzhi Wang; Deming Zhang; Lang Zeng; Erya Deng; Jie Chen 009; Weisheng Zhao 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Ultra-Dense Ring-Shaped Racetrack Memory Cache Design. - Guanda Wang; Yue Zhang 010; Beibei Zhang; Bi Wu 002; Jiang Nan; Xueying Zhang; Zhizhong Zhang 004; Jacques-Olivier Klein; Dafine Ravelosona; Zhaohao Wang; Youguang Zhang; Weisheng Zhao 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

DASM: Data-Streaming-Based Computing in Nonvolatile Memory Architecture for Embedded System. - Liang Chang 002; Xin Ma; Zhaohao Wang; Youguang Zhang; Yufei Ding 001; Weisheng Zhao 001; Yuan Xie 001 (IEEE Trans. Very Large Scale Integr. Syst., 2019)

PXNOR-BNN: In/With Spin-Orbit Torque MRAM Preset-XNOR Operation-Based Binary Neural Networks. - Liang Chang 002; Xin Ma; Zhaohao Wang; Youguang Zhang; Yuan Xie 001; Weisheng Zhao 001 (IEEE Trans. Very Large Scale Integr. Syst., 2019)

An Adaptive Thermal-Aware ECC Scheme for Reliable STT-MRAM LLC Design. - Bi Wu 002; Beibei Zhang; Yuanqing Cheng; Ying Wang 001; Dijun Liu; Weisheng Zhao 001 (IEEE Trans. Very Large Scale Integr. Syst., 2019)

SparseTrain: Exploiting Dataflow Sparsity for Efficient Convolutional Neural Networks Training. - Pengcheng Dai; Jianlei Yang 001; Xucheng Ye; Xingzhou Cheng; Junyu Luo 002; Linghao Song; Yiran Chen 001; Weisheng Zhao 001 (DAC, 2020)

TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture. - Xueyan Wang; Jianlei Yang 001; Yinglin Zhao; Yingjie Qi; Meichen Liu; Xingzhou Cheng; Xiaotao Jia; Xiaoming Chen; Gang Qu 001; Weisheng Zhao 001 (DAC, 2020)

High-Density, Low-Power Voltage-Control Spin Orbit Torque Memory with Synchronous Two-Step Write and Symmetric Read Techniques. - Haotian Wang; Wang Kang 001; Liuyang Zhang; He Zhang 011; Brajesh Kumar Kaushik; Weisheng Zhao 001 (DATE, 2020)

Towards Systems Education for Artificial Intelligence: A Course Practice in Intelligent Computing Architectures. - Jianlei Yang 001; Xiaopeng Gao; Weisheng Zhao 001 (ACM Great Lakes Symposium on VLSI, 2020)

A Novel In-memory Computing Scheme Based on Toggle Spin Torque MRAM. - Yining Bai; Yue Zhang 010; Jinkai Wang; Guanda Wang; Zhizhong Zhang 004; Zhenyi Zheng; Kun Zhang 030; Weisheng Zhao 001 (ACM Great Lakes Symposium on VLSI, 2020)

An In-memory Highly Reconfigurable Logic Circuit Based on Diode-assisted Enhanced Magnetoresistance Device. - Zhe Huang; Yue Zhang 010; Kun Zhang 030; Zhizhong Zhang 004; Jinkai Wang; Youguang Zhang; Weisheng Zhao 001 (ACM Great Lakes Symposium on VLSI, 2020)

Deep Neural Network accelerator with Spintronic Memory. - He Zhang 011; Wang Kang 001; Youguang Zhang; Weisheng Zhao 001 (ACM Great Lakes Symposium on VLSI, 2020)

PRISM: Energy-Efficient Polymorphic Operation Based on Spin-Orbit Torque Memory for Reconfigurable Computing. - Liang Chang 002; Zhaohao Wang; Yang Zhao; Youguang Zhang; Weisheng Zhao 001; Jun Zhou 017 (ISCAS, 2020)

Efficient Time-Domain In-Memory Computing Based on TST-MRAM. - Jinkai Wang; Yue Zhang 010; Chenyu Lian; Yining Bai; Zhe Huang; Guanda Wang; Kun Zhang 030; Youguang Zhang; Weisheng Zhao 001 (ISCAS, 2020)

Computing-in-Memory Architecture Based on Field-Free SOT-MRAM with Self-Reference Method. - Chao Wang 094; Zhaohao Wang; Yansong Xu; Jianlei Yang 001; Youguang Zhang; Weisheng Zhao 001 (ISCAS, 2020)

Voltage-Gated Spin-Hall Effect Based Magnetic Non-Volatile Flip-Flop for High Speed, Low Power and Compact Cell Area. - Kaili Zhang; Deming Zhang; Chengzhi Wang; Lang Zeng; Weisheng Zhao 001 (ISCAS, 2020)

Movable-Type Transfer and Stacking of van der Waals Heterostructures for Spintronics. - Yuan Cao; Xinhe Wang; Xiaoyang Lin; Wei Yang; Chen Lv; Yuan Lu; Youguang Zhang; Weisheng Zhao 001 (IEEE Access, 2020)

A Diode-Enhanced Scheme for Giant Magnetoresistance Amplification and Reconfigurable Logic. - Jiang Nan; Kun Zhang 030; Yue Zhang 010; Shaohua Yan; Zhizhong Zhang 004; Zhenyi Zheng; Guanda Wang; Qunwen Leng; Youguang Zhang; Weisheng Zhao 001 (IEEE Access, 2020)

Compact Modeling and Analysis of Voltage-Gated Spin-Orbit Torque Magnetic Tunnel Junction. - Kaili Zhang; Deming Zhang; Chengzhi Wang; Lang Zeng; You Wang 002; Weisheng Zhao 001 (IEEE Access, 2020)

An STT-MRAM based reconfigurable computing-in-memory architecture for general purpose computing. - Yu Pan; Xiaotao Jia; Zhen Cheng; Peng Ouyang; Xueyan Wang; Jianlei Yang 001; Weisheng Zhao 001 (CCF Trans. High Perform. Comput., 2020)

Prototyping federated learning on edge computing systems. - Jianlei Yang 001; Yixiao Duan; Tong Qiao; Huanyu Zhou; Jingyuan Wang 001; Weisheng Zhao 001 (Frontiers Comput. Sci., 2020)

A Comparative Cross-layer Study on Racetrack Memories: Domain Wall vs Skyrmion. - Wang Kang 001; Bi Wu 002; Xing Chen 012; Daoqian Zhu; Zhaohao Wang; Xichao Zhang; Yan Zhou; Youguang Zhang; Weisheng Zhao 001 (ACM J. Emerg. Technol. Comput. Syst., 2020)

Write Back Energy Optimization for STT-MRAM-based Last-level Cache with Data Pattern Characterization. - Jiacheng Ni; Keren Liu; Bi Wu 002; Weisheng Zhao 001; Yuanqing Cheng; Xiaolong Zhang; Ying Wang 001 (ACM J. Emerg. Technol. Comput. Syst., 2020)

Hardware Security in Spin-based Computing-in-memory: Analysis, Exploits, and Mitigation Techniques. - Xueyan Wang; Jianlei Yang 001; Yinglin Zhao; Xiaotao Jia; Gang Qu 001; Weisheng Zhao 001 (ACM J. Emerg. Technol. Comput. Syst., 2020)

SPINBIS: Spintronics-Based Bayesian Inference System With Stochastic Computing. - Xiaotao Jia; Jianlei Yang 001; Pengcheng Dai; Runze Liu 001; Yiran Chen 001; Weisheng Zhao 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration. - Bi Wu 002; Pengcheng Dai; Yuanqing Cheng; Ying Wang 001; Jianlei Yang 001; Zhaohao Wang; Dijun Liu; Weisheng Zhao 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Design of Magnetic Non-Volatile TCAM With Priority-Decision in Memory Technology for High Speed, Low Power, and High Reliability. - Chengzhi Wang; Deming Zhang; Lang Zeng; Weisheng Zhao 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy. - Bi Wu 002; Weisheng Zhao 001; Xiaobo Sharon Hu; Pengcheng Dai; Zhaohao Wang; Chao Wang 094; Ying Wang 001; Jianlei Yang 001; Yuanqing Cheng; Dijun Liu; Youguang Zhang (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

MTJ-LRB: Proposal of MTJ-Based Loop Replica Bitline as MRAM Device-Circuit Interaction for PVT-Robust Sensing. - Yongliang Zhou; Hao Cai 001; Bo Liu 019; Weisheng Zhao 001; Jun Yang 006 (IEEE Trans. Circuits Syst., 2020)

A Self-Timed Voltage-Mode Sensing Scheme With Successive Sensing and Checking for STT-MRAM. - Yongliang Zhou; Hao Cai 001; Lei Xie; Menglin Han; Mingyue Liu; Shi Xu; Bo Liu 019; Weisheng Zhao 001; Jun Yang 006 (IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020)

Tiny neural network search and implementation for embedded FPGA: a software-hardware co-design approach. - Jinyu Bai; Yunqian Fan; Sifan Sun; Wang Kang 001; Weisheng Zhao 001 (A-SSCC, 2021)

FedSkel: Efficient Federated Learning on Heterogeneous Systems with Skeleton Gradients Update. - Junyu Luo 002; Jianlei Yang 001; Xucheng Ye; Xin Guo 008; Weisheng Zhao 001 (CIKM, 2021)

SpinLiM: Spin Orbit Torque Memory for Ternary Neural Networks Based on the Logic-in-Memory Architecture. - Lichuan Luo; He Zhang 011; Jinyu Bai; Youguang Zhang; Wang Kang 001; Weisheng Zhao 001 (DATE, 2021)

A 40nm 33.6Tops/W 8T-SRAM Computing-in-Memory Macro with DAC-less Spike-Pulse-Truncation Input and ADC-less Charge-Reservoir-Integrate-Counter Output. - He Zhang 011; Junzhan Liu; Wang Kang 001; Yunqian Fan; Shufeng Fu; Jinyu Bai; Biao Pan; Yongpan Liu; Weisheng Zhao 001 (ICTA, 2021)

A Reconfigurable Arbiter PUF Based on STT-MRAM. - Rashid Ali; You Wang 002; Haoyuan Ma; Zhengyi Hou; Deming Zhang; Erya Deng; Weisheng Zhao 001 (ISCAS, 2021)

Spin-Orbit Torque Nonvolatile Flip-Flop Designs. - Erya Deng; Wang Kang 001; Weisheng Zhao 001; Shaoqian Wei; You Wang 002; Deming Zhang (ISCAS, 2021)

SpinSim: A Computer Architecture-Level Variation Aware STT-MRAM Performance Evaluation Framework. - Haoyuan Ma; You Wang 002; Rashid Ali; Zhengyi Hou; Deming Zhang; Erya Deng; Gefei Wang; Weisheng Zhao 001 (ISCAS, 2021)

Computing-in-Memory Paradigm Based on STT-MRAM with Synergetic Read/Write-Like Modes. - Chao Wang 094; Zhaohao Wang; Youguang Zhang; Weisheng Zhao 001 (ISCAS, 2021)

Fully Single Event Double Node Upset Tolerant Design for Magnetic Random Access Memory. - Deming Zhang; Xian Wang; Kaili Zhang; Lang Zeng; You Wang 002; Bi Wang 002; Erya Deng; Chuanjie Wang; Peng Wu; Youguang Zhang; Weisheng Zhao 001 (ISCAS, 2021)

Soft Error Sensitivity of Magnetic Random Access Memory and Its Radiation Hardening Design. - Bi Wang 002; Zhaohao Wang; Min Wang 033; Weisheng Zhao 001; Liang Wang; Yuanfu Zhao (ISOCC, 2021)

A Computing-in-memory Scheme with Series Bit-cell in STT-MRAM for Efficient Multi-bit Analog Multiplication. - Zuolei Hao; Yue Zhang 010; Jinkai Wang; Hongyu Wang; Yining Bai; Guanda Wang; Weisheng Zhao 001 (NANOARCH, 2021)

A Novel Multi-Context Non-Volatile Content-Addressable Memory Cell and Multi-Level Architecture for High Reliability and Density. - Xian Wang; Deming Zhang; Kaili Zhang; Erya Deng; You Wang 002; Weisheng Zhao 001 (NVMSA, 2021)

Brief Industry Paper: optimizing Memory Efficiency of Graph Neural Networks on Edge Computing Platforms. - Ao Zhou; Jianlei Yang 001; Yeqi Gao; Tong Qiao; Yingjie Qi; Xiaoyi Wang; Yunli Chen; Pengcheng Dai; Weisheng Zhao 001; Chunming Hu (RTAS, 2021)

Optimizing Memory Efficiency of Graph Neural Networks on Edge Computing Platforms. - Ao Zhou; Jianlei Yang 001; Yeqi Gao; Tong Qiao; Yingjie Qi; Xiaoyi Wang; Yunli Chen; Pengcheng Dai; Weisheng Zhao 001; Chunming Hu (CoRR, 2021)

S2Engine: A Novel Systolic Architecture for Sparse Convolutional Neural Networks. - Jianlei Yang 001; Wenzhi Fu; Xingzhou Cheng; Xucheng Ye; Pengcheng Dai; Weisheng Zhao 001 (CoRR, 2021)

Forecasting the outcome of spintronic experiments with Neural Ordinary Differential Equations. - Xing Chen 012; Flavio Abreu Araujo; Mathieu Riou; Jacob Torrejon; Dafine Ravelosona; Wang Kang 001; Weisheng Zhao 001; Julie Grollier; Damien Querlioz (CoRR, 2021)

Spintronics for Energy- Efficient Computing: An Overview and Outlook. - Zongxia Guo; Jialiang Yin; Yue Bai; Daoqian Zhu; Kewen Shi; Gefei Wang; Kaihua Cao; Weisheng Zhao 001 (Proc. IEEE, 2021)

Toward Energy-Efficient STT-MRAM Design With Multi-Modes Reconfiguration. - Hao Cai 001; Juntong Chen; Yongliang Zhou; Weisheng Zhao 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A NAND-SPIN-Based Magnetic ADC. - Bi Wu 002; Zhaohao Wang; Yuxuan Li; Ying Wang 001; Dijun Liu; Weisheng Zhao 001; Xiaobo Sharon Hu (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Proposal of High Density Two-Bits-Cell Based NAND-Like Magnetic Random Access Memory. - Zhitai Yu; Yijiao Wang; Zeqing Zhang; Kuiqing He; Lang Zeng; Zhaohao Wang; Weisheng Zhao 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization. - Xiaotao Jia; Jianlei Yang 001; Runze Liu 001; Xueyan Wang; Sorin Dan Cotofana; Weisheng Zhao 001 (IEEE Trans. Neural Networks Learn. Syst., 2021)

Spintronic Solutions for Approximate Computing. - You Wang 002; Hao Cai 001; Kaili Zhang; Bo Wu; Bo Liu 019; Deming Zhang; Weisheng Zhao 001 (Approximate Computing, 2022)

Work-in-Progress: Toward Energy-efficient Near STT-MRAM Processing Architecture for Neural Networks. - Yueting Li 001; Bingluo Zhao; Xinyi Xu; Yundong Zhang; Jun Wang; Weisheng Zhao 001 (CODES+ISSS, 2022)

Eventor: an efficient event-based monocular multi-view stereo accelerator on FPGA platform. - Mingjun Li; Jianlei Yang 001; Yingjie Qi; Meng Dong; Yuhao Yang 008; Runze Liu 001; Weitao Pan; Bei Yu 001; Weisheng Zhao 001 (DAC, 2022)

CP-SRAM: charge-pulsation SRAM marco for ultra-high energy-efficiency computing-in-memory. - He Zhang 011; Linjun Jiang; Jianxin Wu; Tingran Chen; Junzhan Liu; Wang Kang 001; Weisheng Zhao 001 (DAC, 2022)

An In-memory Booth Multiplier Based on Non-volatile Memory for Neural Network Applications. - Jiayao Wu; Yijiao Wang; Zhi Yang 001; Kuiqing He; Pengxu Wang; Weisheng Zhao 001 (NANOARCH, 2022)

Stateful implication logic based on perpendicular magnetic tunnel junctions. - Wenlong Cai; Mengxing Wang 001; Kaihua Cao; Huaiwen Yang; Shouzhong Peng; Huisong Li; Weisheng Zhao 001 (Sci. China Inf. Sci., 2022)

Femtosecond laser-assisted switching in perpendicular magnetic tunnel junctions with double-interface free layer. - Luding Wang; Wenlong Cai; Kaihua Cao; Kewen Shi; Bert Koopmans; Weisheng Zhao 001 (Sci. China Inf. Sci., 2022)

Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture. - Xueyan Wang; Jianlei Yang 001; Yinglin Zhao; Xiaotao Jia; Rong Yin 001; Xuhang Chen 001; Gang Qu 001; Weisheng Zhao 001 (IEEE Trans. Computers, 2022)

S2 Engine: A Novel Systolic Architecture for Sparse Convolutional Neural Networks. - Jianlei Yang 001; Wenzhi Fu; Xingzhou Cheng; Xucheng Ye; Pengcheng Dai; Weisheng Zhao 001 (IEEE Trans. Computers, 2022)

Accelerating Graph-Connected Component Computation With Emerging Processing-In-Memory Architecture. - Xuhang Chen 001; Xueyan Wang; Xiaotao Jia; Jianlei Yang 001; Gang Qu 001; Weisheng Zhao 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Machine Learning Attack-Resilient Strong PUF Leveraging the Process Variation of MRAM. - Rashid Ali; Deming Zhang; Hao Cai 001; Weisheng Zhao 001; You Wang 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Spintronic In-Memory Computing Network for Efficient Hamming Codec Implementation. - Linjun Jiang; Erya Deng; He Zhang 011; Zhaohao Wang; Wang Kang 001; Weisheng Zhao 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Mini Tutorial of Processing in Memory: From Principles, Devices to Prototypes. - Biao Pan; Guangyao Wang; He Zhang 011; Wang Kang 001; Weisheng Zhao 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Toward Energy-Efficient Sparse Matrix-Vector Multiplication with near STT-MRAM Computing Architecture. - Yueting Li 001; He Zhang 011; Xueyan Wang; Hao Cai 001; Yundong Zhang; Shuqin Lv; Renguang Liu; Weisheng Zhao 001 (ASP-DAC, 2023)

TOTAL: Multi-Corners Timing Optimization Based on Transfer and Active Learning. - Wei W. Xing; Zheng Xing; Rongqi Lu; Zhelong Wang; Ning Xu 006; Yuanqing Cheng; Weisheng Zhao 001 (DAC, 2023)

Hardware-Aware Graph Neural Network Automated Design for Edge Computing Platforms. - Ao Zhou; Jianlei Yang 001; Yingjie Qi; Yumeng Shi; Tong Qiao; Weisheng Zhao 001; Chunming Hu (DAC, 2023)

TAM: A Computing in Memory based on Tandem Array within STT-MRAM for Energy-Efficient Analog MAC Operation. - Jinkai Wang; Zhengkun Gu; Hongyu Wang; Zuolei Hao; Bojun Zhang; Weisheng Zhao 001; Yue Zhang 010 (DATE, 2023)

THE-V: Verifiable Privacy-Preserving Neural Network via Trusted Homomorphic Execution. - Yuntao Wei; Xueyan Wang; Song Bian 001; Weisheng Zhao 001; Yier Jin (ICCAD, 2023)

Full reliability characterization of three-terminal SOT-MTJ devices and corresponding arrays. - Xinyi Xu; Hongchao Zhang; Chuanpeng Jiang; Jinhao Li 007; Shiyang Lu; Yunpeng Li; Honglei Du; Xueying Zhang; Zhaohao Wang; Kaihua Cao; Weisheng Zhao 001; Shuqin Lyu; et al. (IRPS, 2023)

TinyFormer: Efficient Transformer Design and Deployment on Tiny Devices. - Jianlei Yang 001; Jiacheng Liao; Fanding Lei; Meichen Liu; Junyi Chen; Lingkun Long; Han Wan; Bei Yu 001; Weisheng Zhao 001 (CoRR, 2023)

A Survey of MRAM-Centric Computing: From Near Memory to In Memory. - Yueting Li 001; Tianshuo Bai; Xinyi Xu; Yundong Zhang; Bi Wu 002; Hao Cai 001; Biao Pan; Weisheng Zhao 001 (IEEE Trans. Emerg. Top. Comput., 2023)

Experimental Demonstration of STT-MRAM-based Nonvolatile Instantly On/Off System for IoT Applications: Case Studies. - Yueting Li 001; Wang Kang 001; Kunyu Zhou; Keni Qiu; Weisheng Zhao 001 (ACM Trans. Embed. Comput. Syst., 2023)

BoA-PTA: A Bayesian Optimization Accelerated PTA Solver for SPICE Simulation. - Wei W. Xing; Xiang Jin; Tian Feng 002; Dan Niu; Weisheng Zhao 001; Zhou Jin 001 (ACM Trans. Design Autom. Electr. Syst., 2023)

NAND-SPIN-based processing-in-MRAM architecture for convolutional neural network acceleration. - Yinglin Zhao; Jianlei Yang 001; Bing Li 017; Xingzhou Cheng; Xucheng Ye; Xueyan Wang; Xiaotao Jia; Zhaohao Wang; Youguang Zhang; Weisheng Zhao 001 (Sci. China Inf. Sci., 2023)

Layout Aware Optimization Methodology for SOT-MRAM Based on Technically Feasible Top-Pinned Magnetic Tunnel Junction Process. - Chao Wang 094; Zhaohao Wang; Zhongkui Zhang; Jiagao Feng; Youguang Zhang; Weisheng Zhao 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Implementation of 16 Boolean logic operations based on one basic cell of spin-transfer-torque magnetic random access memory. - Yan Huang; Kaihua Cao; Kun Zhang 030; Jinkai Wang; Kewen Shi; Zuolei Hao; Wenlong Cai; Ao Du; Jialiang Yin; Qing Yang; Junfeng Li; Jianfeng Gao 005; et al. (Sci. China Inf. Sci., 2023)

IMGA: Efficient In-Memory Graph Convolution Network Aggregation With Data Flow Optimizations. - Yuntao Wei; Xueyan Wang; Shangtong Zhang; Jianlei Yang 001; Xiaotao Jia; Zhaohao Wang; Gang Qu 001; Weisheng Zhao 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Outgoing Editorial. - Weisheng Zhao 001; Hai Helen Li; Domenico Zito (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity. - Cenlin Duan; Jianlei Yang 001; Yiou Wang; Yikun Wang; Yingjie Qi; Xiaolin He; Bonan Yan; Xueyan Wang; Xiaotao Jia; Weisheng Zhao 001 (DAC, 2024)

Series-Parallel Hybrid SOT-MRAM Computing-in-Memory Macro with Multi-Method Modulation for High Area and Energy Efficiency. - Weiliang Huang; Jinyu Bai; Wang Kang 001; Zhaohao Wang; Kaihua Cao; Hongxi Liu; He Zhang 011; Weisheng Zhao 001 (DAC, 2024)

A Combined Content Addressable Memory and In-Memory Processing Approach for k-Clique Counting Acceleration. - Xidi Ma; Weichen Zhang; Xueyan Wang; Tianyang Yu; Bi Wu 002; Gang Qu 001; Weisheng Zhao 001 (DAC, 2024)

GNNavigator: Towards Adaptive Training of Graph Neural Networks via Automatic Guideline Exploration. - Tong Qiao; Jianlei Yang 001; Yingjie Qi; Ao Zhou; Chen Bai; Bei Yu 001; Weisheng Zhao 001; Chunming Hu (DAC, 2024)

FRM-CIM: Full-Digital Recursive MAC Computing in Memory System Based on MRAM for Neural Network Applications. - Jinkai Wang; Zekun Wang; Bojun Zhang; Zhengkun Gu; Youxiang Chen; Weisheng Zhao 001; Yue Zhang 010 (DAC, 2024)

PPGNN: Fast and Accurate Privacy-Preserving Graph Neural Network Inference via Parallel and Pipelined Arithmetic-and-Logic FHE Accelerator. - Yuntao Wei; Xueyan Wang; Song Bian 001; Yicheng Huang; Weisheng Zhao 001; Yier Jin (DAC, 2024)

Graph Neural Networks Automated Design and Deployment on Device-Edge Co-Inference Systems. - Ao Zhou; Jianlei Yang 001; Tong Qiao; Yingjie Qi; Zhi Yang 001; Weisheng Zhao 001; Chunming Hu (DAC, 2024)

LLP-ECCA: A Low-Latency and Programmable Framework for Elliptic Curve Cryptography Accelerators. - Yicheng Huang; Xueyan Wang; Tianao Dai; Jianlei Yang 001; Zhaojun Lu; Xiaotao Jia; Gang Qu 001; Weisheng Zhao 001 (ITC-Asia, 2024)

CRISP: Triangle Counting Acceleration via Content Addressable Memory-Integrated 3D-Stacked Memory. - Shangtong Zhang; Xueyan Wang; Weisheng Zhao 001; Yier Jin (ITC-Asia, 2024)

A Novel Radiation-Hardened Non-volatile Magnetic Latch Circuit. - Jiaxin Yang; Jilong Liu; Lang Zeng; Yue Zhang 010; Weisheng Zhao 001; Deming Zhang (NVMTS, 2024)

Spin-orbit torque efficiency enhancement to tungsten-based SOT-MTJs by interface modification with an ultrathin MgO. - Shiyang Lu; Xiaobai Ning; Hongchao Zhang; Sixi Zhen; Xiaofei Fan; Danrong Xiong; Dapeng Zhu; Gefei Wang; Hongxi Liu; Kaihua Cao; Weisheng Zhao 001 (Sci. China Inf. Sci., 2024)

CiM-BNN:Computing-in-MRAM Architecture for Stochastic Computing Based Bayesian Neural Network. - Huiyi Gu; Xiaotao Jia; Yuhao Liu; Jianlei Yang 001; Xueyan Wang; Youguang Zhang; Sorin Dan Cotofana; Weisheng Zhao 001 (IEEE Trans. Emerg. Top. Comput., 2024)

CIMQ: A Hardware-Efficient Quantization Framework for Computing-In-Memory-Based Neural Network Accelerators. - Jinyu Bai; Sifan Sun; Weisheng Zhao 001; Wang Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory. - Cenlin Duan; Jianlei Yang 001; Xiaolin He; Yingjie Qi; Yikun Wang; Yiou Wang; Ziyan He; Bonan Yan; Xueyan Wang; Xiaotao Jia; Weitao Pan; Weisheng Zhao 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Area and Energy Efficient Short-Circuit-Logic-Based STT-MRAM Crossbar Array for Binary Neural Networks. - Chao Wang 094; Zhaohao Wang; Zhongkui Zhang; Youguang Zhang; Weisheng Zhao 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Charge-Domain Compute-In-Memory Macro With Cell-Embedded DA Conversion and Two-Stage AD Conversion for Bit-Scalable MAC Operation. - Kaili Zhang; Zhongzhen Tong; Xinxin Liang; Chengzhi Wang; You Wang 002; Yue Zhang 010; Weisheng Zhao 001; Lang Zeng; Deming Zhang (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Toward Energy-efficient STT-MRAM-based Near Memory Computing Architecture for Embedded Systems. - Yueting Li 001; Xueyan Wang; He Zhang 011; Biao Pan; Keni Qiu; Wang Kang 001; Jun Wang; Weisheng Zhao 001 (ACM Trans. Embed. Comput. Syst., 2024)

CIM²PQ: An Arraywise and Hardware-Friendly Mixed Precision Quantization Method for Analog Computing-In-Memory. - Sifan Sun; Jinyu Bai; Zhaoyu Shi; Weisheng Zhao 001; Wang Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Multicorner Timing Analysis Acceleration for Iterative Physical Design of ICs. - Wei W. Xing; Longze Wang; Zhelong Wang; Zhaoyu Shi; Ning Xu 006; Yuanqing Cheng; Weisheng Zhao 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

APIM: An Antiferromagnetic MRAM-Based Processing-In-Memory System for Efficient Bit-Level Operations of Quantized Convolutional Neural Networks. - Yueting Li 001; Jinkai Wang; Daoqian Zhu; Jinhao Li 007; Ao Du; Xueyan Wang; Yue Zhang 010; Weisheng Zhao 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

An Energy-Efficient Bayesian Neural Network Implementation Using Stochastic Computing Method. - Xiaotao Jia; Huiyi Gu; Yuhao Liu; Jianlei Yang 001; Xueyan Wang; Weitao Pan; Youguang Zhang; Sorin Cotofana; Weisheng Zhao 001 (IEEE Trans. Neural Networks Learn. Syst., 2024)

HGNAS: Hardware-Aware Graph Neural Architecture Search for Edge Devices. - Ao Zhou; Jianlei Yang 001; Yingjie Qi; Tong Qiao; Yumeng Shi; Cenlin Duan; Weisheng Zhao 001; Chunming Hu (IEEE Trans. Computers, 2024)

BSTCIM: A Balanced Symmetry Ternary Fully Digital In-MRAM Computing Macro for Energy Efficiency Neural Network. - Zhongzhen Tong; Chenghang Li; Chao Wang 094; Suteng Zhao; Qianyong Peng; Zhenyu Yan; Siqi Zhang; Daming Zhou; Zhaohao Wang; Xiaoyang Lin; Weisheng Zhao 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A Custom RISC-V ISA with Scalable Processing Units for Efficient Neural Network Inference. - Yueting Li 001; Wanshuang Lin; Wendong Xu; Ngai Wong 001; Weisheng Zhao 001 (CF, 2025)

MIRACLE: Multimodal Information Retrieval via a Combined In-Memory Processing and Content Addressable Memory Approach. - Xuehui Liu; Xueyan Wang; Tianyang Yu; Chen Cheng; Shuo Ran; Bi Wu 002; Xiaotao Jia; Weiqiang Liu 001; Gang Qu 001; Weisheng Zhao 001 (DAC, 2025)

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures. - Yingjie Qi; Jianlei Yang 001; Yiou Wang; Yikun Wang; Dayu Wang; Ling Tang; Cenlin Duan; Xiaolin He; Weisheng Zhao 001 (DAC, 2025)

An Adaptive Sparse Matrix Compression CIM Accelerator based on 256Kb SOT-MRAM for Downlink Massive MIMO Communications. - Liangchen Li; Jianxin Wu; Changyu Li; Liang Zhang; Anyang Yu; Junda Zhao; Zhaohao Wang; Chengyuan Sun; Kaihua Cao; Hongxi Liu; Wang Kang 001; He Zhang 011; et al. (ICCAD, 2025)

Ultra Energy-Efficient Butterfly Counting in Bipartite Networks via Algorithm-Architecture Co-Optimization. - Haiyang Liu; Xueyan Wang; Jianlei Yang 001; Xiaotao Jia; Gang Qu 001; Weisheng Zhao 001 (ICCAD, 2025)

HRAMTran: A Hybrid-RAM Transformer Accelerator With Dynamic Sparsity Floating-Point CIM and Written-Back Transpose Array. - Bojun Zhang; Jinkai Wang; Xianan Zhu; Ziyuan Guo; Zhengkun Gu; Kaili Zhang; Zhizhong Zhang 004; Kun Zhang 030; Weisheng Zhao 001; Yue Zhang 010 (ICCAD, 2025)

Finesse: An Agile Design Framework for Pairing-based Cryptography via Software/Hardware Co-Design. - Tianwei Pan; Tianao Dai; Jianlei Yang 001; Hongbin Jing; Yang Su; Zeyu Hao; Xiaotao Jia; Chunming Hu; Weisheng Zhao 001 (ISCA, 2025)

Thermal-Compensated MRAM Sensing: Dynamic TMR Stabilization Across Wide Temperature Range. - Tuo Zhang; Xinpeng Jiang; Chao Wang 094; Bi Wang 002; Hongxi Liu; Kaihua Cao; Xuan Li; Hui Jin; Geifei Wang; Zhaohao Wang; He Zhang 011; Weisheng Zhao 001 (MOCAST, 2025)

Model quantization for computing-in-memory: a survey. - Sifan Sun; Jinyu Bai; Hanting Chen; Kaiwen Deng; Zhiwei Xie 009; Jingjing Li; Bin Cao; He Zhang 011; Wang Kang 001; Weisheng Zhao 001 (Sci. China Inf. Sci., 2025)

Orbitronics for energy-efficient magnetization switching. - Yuxuan Yao; Daoqian Zhu; Qingtao Xia; Jianing Liang; Yuhao Jiang; Zhiyang Peng; Jiaxu Li; Chen Xiao; Renyou Xu; Wenwen Wang; Xiantao Shang; Shiyang Lu; et al. (Sci. China Inf. Sci., 2025)

HiT-CIM: A High-Throughput Compute-in-Memory SRAM Architecture With Simultaneous Weight Loading/Computing and Balance Capabilities. - Junzhan Liu; Sifan Sun; Liang Zhang; Lichuan Luo; Liang Ran; He Zhang 011; Wang Kang 001; Weisheng Zhao 001 (IEEE Trans. Emerg. Top. Comput., 2025)

A High-Speed, Low-Power, High-Reliability and Fully Single Event Double Node Upset Tolerant Design for Magnetic Random Access Memory. - Jiaxin Yang; Ziyang Guo; Shixuan Wang; Jilong Liu; Yue Zhang 010; Weisheng Zhao 001; Lang Zeng; Deming Zhang (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

In-MRAM Computing Based on Complementary-Sensing Time-Based Readout Circuit Using Hybrid VGSOT-MTJ/GAA-CNTFET. - Zhongzhen Tong; Sifan Sun; Kaili Zhang; Chenghang Li; Daming Zhou; Zhaohao Wang; Xiaoyang Lin; Weisheng Zhao 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

Technically Feasible Robust Complementary SOT-MRAM Design for Improving the Area and Energy Efficiency. - Chao Wang 094; Zhongkui Zhang; Xiaoyang Xu; Xianzeng Guo; Qihang Gao; Zhaohao Wang; Weisheng Zhao 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Heterogeneous System With Computing in Memory Processing Elements to Accelerate CNN Inference. - Jinkai Wang; Youxiang Chen; Zekun Wang; Zhengkun Gu; Bojun Zhang; Haiming Qiu; Kun Zhang 030; Weisheng Zhao 001; Yue Zhang 010 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

MS-SCIM: A Mixed-Signal Stochastic Computing-in-Memory Paradigm for Information Security. - Pengxu Wang; Yijiao Wang; Jialiang Yin; Jiayao Wu; Xinrui Duan; Yaqi Wang; Zhaohao Wang; Weisheng Zhao 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Temperature-Resilient Reconfigurable PUF with Dual-Pulse Modulation based on SOT-MRAM Chip. - Min Wang 033; Chuanpeng Jiang; Zhaohao Wang; Zhengyi Hou; Zhongkui Zhang; Yuanfu Zhao; Hongxi Liu; Weisheng Zhao 001 (CoRR, 2025)

HPIM: Heterogeneous Processing-In-Memory-based Accelerator for Large Language Models Inference. - Cenlin Duan; Jianlei Yang 001; Rubing Yang; Yikun Wang; Yiou Wang; Lingkun Long; Yingjie Qi; Xiaolin He; Ao Zhou; Xueyan Wang; Weisheng Zhao 001 (CoRR, 2025)

A Time and Energy-Efficient Asynchronous Hybrid-Searching Auto Frequency Calibration for a 3.2 GHz Phase-Locked Loop. - Zijie Wang; Fanxun Cai; Lianbo Wu; Hui Zhang; Weisheng Zhao 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Self-Decryption Pass Transistor Logic-Based In-MRAM Computing Macro Using Hybrid VGSOT-MTJ/GAA-CNTFET. - Zhongzhen Tong; Sifan Sun; Kaili Zhang; Chenghang Li; Jiye Yao; Yulong Qiu; Chao Wang 094; Zhaohao Wang; Ke Zhang; Amara Amara; Xiaoyang Lin; Weisheng Zhao 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A 0.88 e‾rms 8-Mpixel 3D-Stacked Low Temporal-Noise CMOS Image Sensor With Auto-Zero Single-Slope ADC, Fast Correlated Multi-Sampling, Row-Wise Noise Reduction, and Dark Current Non-Uniformity Calibration Techniques. - Jianxin Wu; Wenjie Li; Wang Kang 001; Jing Kou; Liang Zhang; Liangchen Li; He Zhang 011; Weisheng Zhao 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A 32 kb 55 nm Radiation-Hardened SRAM Chip With SEU ≤1.1 E-11 Upsets/Bit-Day, SEL >107.1 MeV ⋅ cm²/mg, and TID >100 Krad(Si) for Space Applications. - Deming Zhang; Jiaxin Yang; Dingyi Luo; Jianpeng Zhang; Lang Zeng; Bi Wang 002; Yue Zhang 010; Weisheng Zhao 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

AM-CIM: Approximate Memory Based Near Sensor Compute-in-Memory Architecture for Keyword Spotting. - Yuhao Liu; Xiaotao Jia; Guangcai Yuan; Jianyi Yu; Cong Shi 003; Qi Wei 001; Youguang Zhang; Weisheng Zhao 001; Fei Qiao (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

An Effective SNN Macro with Real-Time STDP and Dynamic LIF Model Based on Thermally Interplayed Spin-Orbit Torque MTJ. - Changyu Li; Linjun Jiang; Liangchen Li; Dehang Zhu; Junda Zhao; Hongxi Liu; Wang Kang 001; Wenlong Cai; He Zhang 011; Weisheng Zhao 001 (DATE, 2026)

Late Breaking Results: Algorithm-Hardware Co-Design of a Sparsity-Aware Dense-Sparse Scheme for DNN Accelerators. - Yueting Li 001; Zhen Li; Terry Tao Ye; Weisheng Zhao 001 (DATE, 2026)

Input Sparsity Aware In-Memory Computing Macro Based on SOT-MRAM Multi-Level Cell for Efficient Deep Neural Network Acceleration. - Chao Wang 094; Qihang Gao; Xianzeng Guo; Zhongzhen Tong; Zhaohao Wang; Weisheng Zhao 001 (DATE, 2026)

High-Performance and High-Density NAND-Like SOT-MRAM for FinFET Technology Nodes. - Chao Wang 094; Xianzeng Guo; Luman Xiang; Zhaohao Wang; Weisheng Zhao 001 (DATE, 2026)

High-performance true random number generator based on SOT-MTJ spin relaxation. - Jialiang Yin; Xiuye Zhang; Boyan Zhang; Bolin Zhang; Wenlong Cai; Ao Du; Binchao Tang; Haowei Zhang; Shijian Bao; Chunyi Li; Daoqian Zhu; Kewen Shi; et al. (Sci. China Inf. Sci., 2026)

CIMinus: Empowering Sparse DNN Workloads Modeling and Exploration on SRAM-Based CIM Architectures. - Yingjie Qi; Jianlei Yang 001; Rubing Yang; Cenlin Duan; Xiaolin He; Ziyan He; Weitao Pan; Weisheng Zhao 001 (IEEE Trans. Computers, 2026)

GCoDE: Efficient Device-Edge Co-Inference for GNNs via Architecture-Mapping Co-Search. - Ao Zhou; Jianlei Yang 001; Tong Qiao; Yingjie Qi; Zhi Yang 001; Weisheng Zhao 001; Chunming Hu (IEEE Trans. Computers, 2026)

Efficient SRAM-PIM Co-Design by Joint Exploration of Value-Level and Bit-Level Sparsity. - Cenlin Duan; Jianlei Yang 001; Yikun Wang; Yiou Wang; Yingjie Qi; Xiaolin He; Bonan Yan; Xueyan Wang; Xiaotao Jia; Weisheng Zhao 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2026)

An FD-SOI-Based Compact In-Pixel Computing Architecture Enabling Real-Time Feature Extraction. - Yijiao Wang; Jiayao Wu; Yaqi Wang; Zhongzhen Tong; Xinrui Duan; Yiming Shi; Wen Shi; Weisheng Zhao 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2026)

NFGen: Normalizing Flow-Based Joint Generative Model for Variability-Aware Design Technology Co-Optimization. - Tao Zou; Zhenxing Dou; Zhiwei Chen; Yijiao Wang; Wen Shi; Zhiyu Wang; Peng Wang 022; Runsheng Wang; Weisheng Zhao 001; Asen Asenov (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2026)

ReNN-RV: Run-Time PE Reconfiguration for DNN Inference Acceleration With Custom RISC-V ISA. - Yueting Li 001; Terry Tao Ye; Ngai Wong 001; Zhenhua Zhu 002; Yongfu Li 002; Weisheng Zhao 001 (IEEE Trans. Computers, 2026)

ACE-GNN: Adaptive GNN Co-Inference With System-Aware Scheduling in Dynamic Edge Environments. - Ao Zhou; Jianlei Yang 001; Tong Qiao; Yingjie Qi; Xinming Wei; Cenlin Duan; Weisheng Zhao 001; Chunming Hu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2026)

BaM-CIM: A High Throughput Booth Algorithm-Based In-MRAM Computing Macro Using Hybrid VGSOT-MTJ/GAA-CNTFET. - Chenghang Li; Zhongzhen Tong; Yulong Qiu; Jiye Yao; Chao Wang 094; Zhaohao Wang; Xiaoyang Lin; Weisheng Zhao 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2026)

TinyFormer: Efficient Sparse Transformer Design and Deployment on Tiny Devices. - Jianlei Yang 001; Jiacheng Liao; Fanding Lei; Meichen Liu; Lingkun Long; Junyi Chen; Han Wan; Bei Yu 001; Weisheng Zhao 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2026)

High-Efficiency and Low-Deviation Analog-Digital Hybrid Compute-in-Memory Architecture With Dynamic Weight Division. - Jianxin Wu; Linjun Jiang; Sifan Sun; Wente Yi; Yitong Zhou; Zhenyu Huang; Dengwen Li; Wang Kang 001; He Zhang 011; Weisheng Zhao 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2026)