Dual priority congestion aware shared-resource Network-on-Chip architecture. - Hao Shu; Jiangyi Shi; Peijun Ma; Huaxi Gu; Weitao Pan; Lin-An Yang (IEICE Electron. Express, 2016)

Analyzing the Impact of Redundant Paths on Multistage Switch Performance. - Ya Gao 003; Weitao Pan; Ling Zheng (ChinaCom (1), 2017)

Improved analytical model for performance evaluation of crosspoint-queued switch under uniform traffic. - Ya Gao 003; Weitao Pan; Ling Zheng (IET Networks, 2017)

A High-Speed Large-Capacity Packet Buffer Scheme for High-Bandwidth Switches and Routers. - Ling Zheng; Zhiliang Qiu; Weitao Pan; Ya Gao 003 (ChinaCom, 2018)

The Design and Implementation of IEEE 1588v2 Clock Synchronization System by Generating Hardware Timestamps in MAC Layer. - Meng Dong; Zhiliang Qiu; Weitao Pan; Can Chen; Junxiang Zhang; Dong Zhang (CITS, 2018)

Research on Model of Five-level Scheduling Based on SDN. - Weitao Pan; Lili Gao; Ling Zheng; Zhiliang Qiu; Junxiang Zhang; Dong Zhang; Ya Gao 003 (CITS, 2018)

The High Speed Packet Classification Supporting Multi - Field for Flow Tables in OpenFlow. - Zhiliang Qiu; Weina Wang 006; Shiyong Sun; Weitao Pan; Ling Zheng; Ya Gao 003; Zhiyi Zhang (CITS, 2018)

Analysis of a Shared-Private Buffer Management Scheme for Shared Memory Switches. - Ling Zheng; Zhiliang Qiu; Weitao Pan; Ya Gao 003; Junxiang Zhang; Dong Zhang (CITS, 2018)

Analysis and Implementation of a QoS Optimization Method for Access Networks. - Ling Zheng; Zhiliang Qiu; Weitao Pan; Yibo Mei; Shiyong Sun; Zhiyi Zhang (IEICE Trans. Commun., 2018)

Design and analysis of a parallel hybrid memory architecture for per-flow buffering in high-speed switches and routers. - Ling Zheng; Zhiliang Qiu; Shiyong Sun; Weitao Pan; Ya Gao 003; Zhiyi Zhang (J. Commun. Networks, 2018)

AFBV: A High-Performance Network Flow Classification Method for Multi-Dimensional Fields and FPGA Implementation. - Ling Zheng; Zhiliang Qiu; Weina Wang 006; Weitao Pan; Shiyong Sun; Ya Gao 003 (J. Circuits Syst. Comput., 2019)

Dual-Plane Switch Architecture for Time-Triggered Ethernet. - Meng Dong; Zhiliang Qiu; Weitao Pan; Hongbin Zhang; Chenglei Kong; Hui Jin; Jianlei Yang 001 (ACM Great Lakes Symposium on VLSI, 2020)

High-Performance and Range-Supported Packet Classification Algorithm for Network Security Systems in SDN. - Ling Zheng; Jing Jiang; Weitao Pan; Huan Liu 021 (ICC Workshops, 2020)

Performance analysis and hardware implementation of a nearly optimal buffer management scheme for high-performance shared-memory switches. - Ling Zheng; Weitao Pan; Yinghua Li; Ya Gao 003 (Int. J. Commun. Syst., 2020)

HyperParser: A High-Performance Parser Architecture for Next Generation Programmable Switch and SmartNIC. - Huan Liu 021; Zhiliang Qiu; Weitao Pan; Jiajun Li; Jinjian Huang (APNet, 2021)

Combined Shared-Memory and Buffered-Crossbar Architecture for High-Bandwidth Onboard Switching Fabric. - Ling Zheng; Chen Yi; Weitao Pan; Huan Liu 021 (APNet, 2021)

Design and Implementation of AS6802 Clock Synchronization System in TTE thernet. - Jinlong Dong; Zhiliang Qiu; Weitao Pan; Min Wu; Jialiang Cao (ICCCS, 2021)

Design of HIMAC Coprocessor for HINOC3.0. - Jinjian Huang; Zhiliang Qiu; Weitao Pan; Jun Li; Zhikai Gao; Bing Han; Zihao Xiong; Meng Dong (ICCCS, 2021)

GGTS: FPGA-Based General Ground Test System for Space-Borne Equipment. - Jialu Mang; Zhiliang Qiu; Weitao Pan; Meng Dong; Min Wu (ICCCS, 2021)

Architecture design and performance analysis of a novel memory system for high-bandwidth onboard switching fabric. - Ling Zheng; Weitao Pan; Ya Gao 003; Huan Liu 021; Jing Jiang (Comput. Networks, 2021)

Low-Cost and Programmable CRC Implementation Based on FPGA. - Huan Liu 021; Zhiliang Qiu; Weitao Pan; Jun Li; Ling Zheng; Ya Gao 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Hardware Trojan Designs Based on High-Low Probability and Partitioned Combinational Logic With a Malicious Reset Signal. - Jiangyi Shi; Xinyuan Zhang; Peijun Ma; Weitao Pan; Pengfei Li; Zhengguang Tang (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Eventor: an efficient event-based monocular multi-view stereo accelerator on FPGA platform. - Mingjun Li; Jianlei Yang 001; Yingjie Qi; Meng Dong; Yuhao Yang; Runze Liu 001; Weitao Pan; Bei Yu 001; Weisheng Zhao (DAC, 2022)

A Universal, Low-Delay, SEC-DEC-TAEC Code for State Register Protection. - Meng Dong; Weitao Pan; Zhiliang Qiu; Xiaoxin Qi; Ling Zheng; Huan Liu 021 (IEEE Access, 2022)

Evaluation Method for Feature Selection in Proton Exchange Membrane Fuel Cell Fault Diagnosis. - Lei Mao; Zhongyong Liu; Derek Low; Weitao Pan; Qingbo He; Lisa M. Jackson; Qiang Wu (IEEE Trans. Ind. Electron., 2022)

A Machine Learning Based Approach to Detect Machine Learning Design Patterns. - Weitao Pan; Hironori Washizaki; Nobukazu Yoshioka; Yoshiaki Fukazawa; Foutse Khomh; Yann-Gaël Guéhéneuc (APSEC, 2023)

A unioned graph neural network based hardware Trojan node detection. - Weitao Pan; Meng Dong; Cong Wen; Hongjin Liu; Shaolin Zhang; Bo Shi; Zhixiong Di; Zhiliang Qiu; Yiming Gao 012; Ling Zheng (IEICE Electron. Express, 2023)

Access mechanism for period flows of non-deterministic end systems for time-sensitive networks. - Zhe Zhao; Lu Gao; Weitao Pan; Zhiliang Qiu; Xu Guo; Ya Gao 003; Ling Zheng (Comput. Networks, 2023)

Design and implementation of a frame preemption model without guard bands for time-sensitive networking. - Zhe Zhao; Zhiliang Qiu; Weitao Pan; Hui Li; Ling Zheng; Ya Gao 003 (Comput. Networks, 2024)

DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory. - Cenlin Duan; Jianlei Yang 001; Xiaolin He; Yingjie Qi; Yikun Wang; Yiou Wang; Ziyan He; Bonan Yan; Xueyan Wang; Xiaotao Jia; Weitao Pan; Weisheng Zhao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

An Energy-Efficient Bayesian Neural Network Implementation Using Stochastic Computing Method. - Xiaotao Jia; Huiyi Gu; Yuhao Liu; Jianlei Yang 001; Xueyan Wang; Weitao Pan; Youguang Zhang; Sorin Cotofana; Weisheng Zhao (IEEE Trans. Neural Networks Learn. Syst., 2024)

GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features. - Peijun Ma; Ge Shang; Hongjin Liu; Jiangyi Shi; Weitao Pan; Yan Zhang; Yue Hao 001 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Corrections to "GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features". - Peijun Ma; Ge Shang; Hongjin Liu; Jiangyi Shi; Weitao Pan; Yan Zhang; Yue Hao 001 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Hardware Trojan Detection Methods for Gate-Level Netlists Based on Graph Neural Networks. - Peijun Ma; Jie Li; Hongjin Liu; Jiangyi Shi; Shaolin Zhang; Weitao Pan; Yue Hao 001 (IEEE Trans. Computers, 2025)

Design of a Timer Queue Supporting Dynamic Update Operations. - Zekun Wang; Binghao Yue; Weitao Pan; Jiangyi Shi; Yue Hao 001 (CoRR, 2025)