Estimating rotation speed from projections in SAR. - Weitong Chuang; Thomas S. Huang (ICASSP, 1992)

A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area. - Weitong Chuang; Sachin S. Sapatnekar; Ibrahim N. Hajj (ICCAD, 1993)

Fast Mixed-Mode Simulation for Accurate MOS Bridging Fault Detection. - Weitong Chuang; Ibrahim N. Hajj (ISCAS, 1993)

Delay and area optimization for compact placement by gate resizing and relocation. - Weitong Chuang; Ibrahim N. Hajj (ICCAD, 1994)

Power vs. delay in gate sizing: conflicting objectives? - Sachin S. Sapatnekar; Weitong Chuang (ICCAD, 1995)

Timing and area optimization for standard-cell VLSI circuit design. - Weitong Chuang; Sachin S. Sapatnekar; Ibrahim N. Hajj (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Circuit-level dictionaries of CMOS bridging faults. - Terry Lee; Weitong Chuang; Ibrahim N. Hajj; W. Kent Fuchs (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Power-delay optimizations in gate sizing. - Sachin S. Sapatnekar; Weitong Chuang (ACM Trans. Design Autom. Electr. Syst., 2000)