Weiwei Chen

Affiliations:
  • University of California, Irvine, Center for Embedded Computer Systems, CA, USA (PhD 2013)


According to our database1, Weiwei Chen authored at least 14 papers between 2009 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2014
Out-of-Order Parallel Discrete Event Simulation for Transaction Level Models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

May-happen-in-parallel analysis based on segment graphs for safe ESL models.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Advances in Parallel Discrete Event Simulation for Electronic System-Level Design.
IEEE Des. Test, 2013

Designer-in-the-loop recoding of ESL models using static parallel access conflict analysis.
Proceedings of the International Workshop on Software and Compilers for Embedded Systems, 2013

Optimized out-of-order parallel discrete event simulation using predictions.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Eliminating race conditions in system-level models by using parallel simulation infrastructure.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

Out-of-order parallel simulation for ESL design.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Parallel discrete event simulation of Transaction Level Models.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

An optimizing compiler for out-of-order parallel ESL simulation exploiting instance isolation.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Multicore Simulation of Transaction-Level Models Using the SoC Environment.
IEEE Des. Test Comput., 2011

Multi-core parallel simulation of System-level Description Languages.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
ESL design and multi-core validation using the System-on-Chip Environment.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

A fast heuristic scheduling algorithm for periodic ConcurrenC models.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
ConcurrenC: A New Approach towards Effective Abstraction of C-Based SLDLs.
Proceedings of the Analysis, 2009


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