VLSI Implementation of a Self-tuning Fuzzy Controller Based on Variable Universe of Discourse. - Weiwei Shan; Dongming Jin; Weiwei Jin; Zhihao Xu (FSKD (1), 2005)

Analog Circuit Implementation of a Variable Universe Adaptive Fuzzy Logic Controller. - Weiwei Shan; Yuan Ma; Robert W. Newcomb; Dongming Jin (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Adaptive Fuzzy Logic Controller and Its Application in MEMS Mirror Actuation Feedback Control. - Weiwei Shan; Xiqun Zhu; Yuan Ma (IDEAL, 2009)

Cmos Circuit Design of a Takagi-Sugeno Fuzzy Logic Controller. - Weiwei Shan; Yan Liang; Dongming Jin (J. Circuits Syst. Comput., 2009)

A Novel Combined Proportional-Derivative Control for Electrostatic MEMS Mirror Actuation. - Weiwei Shan; Xin Chen 039 (IEICE Trans. Electron., 2011)

Configuration Cache Management for Coarse-Grained Reconfigurable Architecture with Multi-Array. - Peng Cao 002; Yong Cai; Bo Liu 019; Weiwei Shan (CyberC, 2012)

Memory Bandwidth Optimization Strategy of Coarse-Grained Reconfigurable Architecture. - Peng Cao 002; Huiyan Jiang; Bo Liu 019; Weiwei Shan (CyberC, 2012)

A New Approach to Implement Discrete Wavelet Transform on Coarse-Grained Reconfigurable Architecture. - Jie Li; Xinxiang Ke; Peng Cao 002; Weiwei Shan (CyberC, 2012)

Uniform SystemC Co-Simulation Methodology for System-on-Chip Designs. - Xuexiang Wang; Weiwei Shan; Hao Liu (CyberC, 2012)

A Power Analysis Resistant DES Cryptographic Algorithm and Its Hardware Design. - Jie Li; Yuxiang Lv; Huafang Sun; Weiwei Shan (ICDMA, 2012)

On-chip long-term jitter measurement for PLL based on undersampling technique. - Zhikuang Cai; Haobo Xu; Shixuan Que; Weiwei Shan; Jun Yang 006 (IEICE Electron. Express, 2013)

BIST design of power switch. - Xin Chen 039; Ning Wu; Wei Hu; Weiwei Shan (IEICE Electron. Express, 2013)

An improved timing monitor for deep dynamic voltage scaling system. - Weiwei Shan; Haolin Gu; Bo Li 033; Xiaoqing Wu; Haikun Jin; Yintao Guo; Peng Cao 002 (IEICE Electron. Express, 2013)

Implementation of correlation power analysis attack on an FPGA DES design. - Jun Yang 006; Weiwei Shan; Junyin Liu; Huafang Sun (Int. J. Inf. Commun. Technol., 2013)

Evaluation of Correlation Power Analysis Resistance and Its Application on Asymmetric Mask Protected Data Encryption Standard Hardware. - Weiwei Shan; Xin Chen 039; Bo Li 033; Peng Cao 002; Jie Li; Gugang Gao; Longxing Shi (IEEE Trans. Instrum. Meas., 2013)

Timing error prediction based adaptive voltage scaling for dynamic variation tolerance. - Weiwei Shan; Zhipeng Xu (APCCAS, 2014)

A Side-channel Analysis Resistant Reconfigurable Cryptographic Coprocessor Supporting Multiple Block Cipher Algorithms. - Weiwei Shan; Longxing Shi; Xingyuan Fu; Xiao Zhang; Chaoxuan Tian; Zhipeng Xu; Jun Yang 006; Jie Li (DAC, 2014)

VLSI design of a reconfigurable S-box based on memory sharing method. - Weiwei Shan; Xiao Zhang; Xingyuan Fu; Peng Cao 002 (IEICE Electron. Express, 2014)

A Secure Reconfigurable Crypto IC With Countermeasures Against SPA, DPA, and EMA. - Weiwei Shan; Xingyuan Fu; Zhipeng Xu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Timing monitoring paths selection for wide voltage IC. - Weiwei Shan; Wentao Dai; Youhua Shi; Peng Cao 002; Xiaoyan Xiang (IEICE Electron. Express, 2016)

HTD: A light-weight holosymmetrical transition detector based in-situ timing monitoring technique for wide-voltage-range in 40nm CMOS. - Wentao Dai; Weiwei Shan; Xinning Liu; Jun Yang 006 (A-SSCC, 2017)

A 0.44V-1.1V 9-transistor transition-detector and half-path error detection technique for low power applications. - Xinchao Shang; Weiwei Shan; Longxing Shi; Xing Wan; Jun Yang 006 (A-SSCC, 2017)

In-Situ Timing Monitor-Based Adaptive Voltage Scaling System for Wide-Voltage-Range Applications. - Weiwei Shan; Longxing Shi; Jun Yang 006 (IEEE Access, 2017)

An improved timing error prediction monitor for wide adaptive frequency scaling. - Weiwei Shan; Xinning Liu; Minyi Lu; Shuai Shao; Zhikuang Cai; Jun Yang 006 (IEICE Electron. Express, 2017)

A 0.46V-1.1V Transition-Detector with In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in AES Accelerator. - Xinchao Shang; Weiwei Shan; Jiaming Xu; Minyi Lu; Yiming Xiang; Longxing Shi; Jun Yang 006 (A-SSCC, 2018)

Short-path Padding Method for Timing Error Resilient Circuits based on Transmission Gates Insertion. - Wentao Dai; Peiye Liu; Weiwei Shan (ACM Great Lakes Symposium on VLSI, 2018)

Enabling Resilient Voltage-Controlled MeRAM Using Write Assist Techniques. - Hao Cai 001; You Wang 002; Wang Kang 001; Lirida A. B. Naviner; Weiwei Shan; Jun Yang 006; Weisheng Zhao (ISCAS, 2018)

Correlation-Based Electromagnetic Analysis Attack Using Haar Wavelet Reconstruction with Low-Pass Filtering on an FPGA Implementaion of AES. - Aiguo Bu; Wentao Dai; Minyi Lu; Hao Cai 001; Weiwei Shan (TrustCom/BigDataSE, 2018)

A Compact, Lightweight and Low-Cost 8-Bit Datapath AES Circuit for IoT Applications in 28nm CMOS. - Minyi Lu; Ao Fan; Jiaming Xu; Weiwei Shan (TrustCom/BigDataSE, 2018)

Differential Power Analysis of 8-Bit Datapath AES for IoT Applications. - Jiaming Xu; Ao Fan; Minyi Lu; Weiwei Shan (TrustCom/BigDataSE, 2018)

A Low-Overhead Timing Monitoring Technique for Variation-Tolerant Near-Threshold Digital Integrated Circuits. - Weiwei Shan; Xinning Liu; Minyi Lu; Liang Wan; Jun Yang 006 (IEEE Access, 2018)

Design and Implementation of a Reconfigurable Cryptographic Coprocessor with Multiple Side-Channel Attacks Countermeasures. - Xinchao Shang; Weiwei Shan; Xinning Liu (J. Circuits Syst. Comput., 2018)

HTD: A Light-Weight Holosymmetrical Transition Detector for Wide-Voltage-Range Variation Resilient ICs. - Wentao Dai; Weiwei Shan; Xinchao Shang; Xinning Liu; Hao Cai 001; Jun Yang 006 (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Timing Error Prediction AVFS With Detection Window Tuning for Wide-Operating-Range ICs. - Weiwei Shan; Xinchao Shang; Longxing Shi; Wentao Dai; Jun Yang 006 (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Low Overhead, Within-a-Cycle Adaptive Clock Stretching Circuit With Wide Operating Range in 40-nm CMOS. - Weiwei Shan; Liang Wan; Xinning Liu; Xinchao Shang; Wentao Dai; Shuai Shao; Jun Yang 006; Longxing Shi (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Depthwise Separable Convolution Neural Network for Small-footprint Keyword Spotting Using Approximate MAC Unit and Streaming Convolution Reuse. - Yicheng Lu; Weiwei Shan; Jiaming Xu (APCCAS, 2019)

Successive Stripe Artifact Removal Based on Robust PCA for Millimeter Wave Automotive Radar Image. - Weiwei Shan; Shogo Muramatsu; Akira Oshima; Hiroyoshi Yamada (APSIPA, 2019)

Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOI. - Hao Cai 001; Menglin Han; Weiwei Shan; Jun Yang 006; You Wang 002; Wang Kang 001; Weisheng Zhao (ACM Great Lakes Symposium on VLSI, 2019)

An Energy-Efficient In-Memory BNN Architecture With Time-Domain Analog and Digital Mixed-Signal Processing. - Tao Wang; Weiwei Shan (NANOARCH, 2019)

ynamic Adaptation of Approximate Bit-width for CNNs based on Quantitative Error Resilience. - Chengjun Wu; Weiwei Shan; Jiaming Xu (NANOARCH, 2019)

A 923 Gbps/W, 113-Cycle, 2-Sbox Energy-efficient AES Accelerator in 28nm CMOS. - Weiwei Shan; Ao Fan; Jiaming Xu; Jun Yang 006; Mingoo Seok (VLSI Circuits, 2019)

Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration. - Hao Cai 001; You Wang 002; Lirida Alves de Barros Naviner; Xinning Liu; Weiwei Shan; Jun Yang 006; Weisheng Zhao (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Wide-Voltage-Range Half-Path Timing Error-Detection System With a 9-Transistor Transition-Detector in 40-nm CMOS. - Weiwei Shan; Xinchao Shang; Xing Wan; Hao Cai 001; Chuan Zhang 001; Jun Yang 006 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

An Energy-Efficient Time-Domain Binary Neural Network Accelerator with Error-Detection in 28nm CMOS. - Yuxuan Du; Xinchao Shang; Weiwei Shan (APCCAS, 2020)

Design of Approximate Complex Constant Multiplier for Fast Fourier Transform in 28nm CMOS. - Lixuan Zhu; Lixing Li; Weiwei Shan (ICTA, 2020)

Using Wind Turbines for Providing Defined Levels of Synthetic Inertia in System Split Scenarios. - Martin Shan; Daniel Duckwitz; Weiwei Shan (ISGT-Europe, 2020)

14.1 A 510nW 0.41V Low-Memory Low-Computation Keyword-Spotting Chip Using Serial FFT-Based MFCC and Binarized Depthwise Separable Convolutional Neural Network in 28nm CMOS. - Weiwei Shan; Minhao Yang; Jiaming Xu; Yicheng Lu; Shuai Zhang; Tao Wang; Jun Yang 006; Longxing Shi; Mingoo Seok (ISSCC, 2020)

A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System. - Weiwei Shan; Wentao Dai; Liang Wan; Minyi Lu; Longxing Shi; Mingoo Seok; Jun Yang 006 (IEEE J. Solid State Circuits, 2020)

TG-SPP: A One-Transmission-Gate Short-Path Padding for Wide-Voltage-Range Resilient Circuits in 28-nm CMOS. - Weiwei Shan; Wentao Dai; Chuan Zhang 001; Hao Cai 001; Peiye Liu; Jun Yang 006; Longxing Shi (IEEE J. Solid State Circuits, 2020)

Machine Learning Assisted Side-Channel-Attack Countermeasure and Its Application on a 28-nm AES Circuit. - Weiwei Shan; Shuai Zhang; Jiaming Xu; Minyi Lu; Longxing Shi; Jun Yang 006 (IEEE J. Solid State Circuits, 2020)

A Wide-Voltage-Range Transition-Detector With In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in 28 nm CMOS. - Xinchao Shang; Minyi Lu; Chengjun Wu; Yiming Xiang; Jiaming Xu; Weiwei Shan (IEEE Trans. Circuits Syst., 2020)

An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator without Accuracy Loss in 28nm CMOS. - Ziyu Li; Weiwei Shan; Chengjun Wu; Haitao Ge; Jun Yang 006 (A-SSCC, 2021)

AAD-KWS: a sub-µW keyword spotting chip with a zero-cost, acoustic activity detector from a 170nW MFCC feature extractor in 28nm CMOS. - Lixuan Zhu; Weiwei Shan; Jiaming Xu; Yicheng Lu (ESSCIRC, 2021)

AAD-KWS: a sub-$ mu mathrm{W}$ keyword spotting chip with a zero-cost, acoustic activity detector from a 170nW MFCC feature extractor in 28nm CMOS. - Lixuan Zhu; Weiwei Shan; Jiaming Xu; Yicheng Lu (ESSDERC, 2021)

Energy-Efficient Design of Large Fan-in Dynamic One-hot Multiplexer in 28nm CMOS Technology. - Yuqiang Cui; Chengjun Wu; Ziyu Li; Weiwei Shan (ICTA, 2021)

Design of an ultra-low Power MFCC Feature Extraction Circuit with Embedded Speech Activity Detector. - Kaiyue Yang; Lixuan Zhu; Weiwei Shan (ICTA, 2021)

A 510-nW Wake-Up Keyword-Spotting Chip Using Serial-FFT-Based MFCC and Binarized Depthwise Separable CNN in 28-nm CMOS. - Weiwei Shan; Minhao Yang; Tao Wang; Yicheng Lu; Hao Cai 001; Lixuan Zhu; Jiaming Xu; Chengjun Wu; Longxing Shi; Jun Yang 006 (IEEE J. Solid State Circuits, 2021)

Nanowatt Acoustic Inference Sensing Exploiting Nonlinear Analog Feature Extraction. - Minhao Yang; Hongjie Liu; Weiwei Shan; Jun Zhang; Ilya Kiselev; Sang Joon Kim; Christian C. Enz; Mingoo Seok (IEEE J. Solid State Circuits, 2021)

A Time-Domain Binary CNN Engine With Error-Detection-Based Resilience in 28nm CMOS. - Zhikuang Cai; Boyang Cheng; Yuxuan Du; Xinchao Shang; Weiwei Shan (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A High-Precision PVT-Tolerance Adaptive Clock Circuit Over Wide Frequencies in 28nm CMOS. - Yuqiang Cui; Weiwei Shan (APCCAS, 2022)

An Energy-Efficient Cardiac Arrhythmia Classification Processor using Heartbeat Difference based Classification and Event-Driven Neural Network Computation with Adaptive Wake-Up. - Jiahao Liu; Jianbiao Xiao; Jiajing Fan; Qingsong Liu; Zixuan Zhu 001; Sixu Li; Zhaomin Zhang; Siqi Yang 002; Weiwei Shan; Shuisheng Lin; Liang Chang 002; Liang Zhou; et al. (CICC, 2022)

An energy-efficient seizure detection processor using event-driven multi-stage CNN classification and segmented data processing with adaptive channel selection. - Jiahao Liu; Zirui Zhong; Yong Zhou; Hui Qiu; Jianbiao Xiao; Jiajing Fan; Zhaomin Zhang; Sixu Li; Yiming Xu; Siqi Yang 002; Weiwei Shan; Shuisheng Lin; et al. (DAC, 2022)

A 28nm, 4.69TOPS/W Training, 2.34µJ/lmage Inference, on-chip Training Accelerator with Inference-compatible Back Propagation. - Haitao Ge; Weiwei Shan; Yicheng Lu; Jun Yang 006 (ICTA, 2022)

A Voltage Error Quantizer For Digital Low Dropout Regulators With Fast Transient Response and Low Steady-State Error. - Kaize Zhou; Dejian Li; Chongfei Shen; Yuxuan Du; Zhuo Chen; Weiwei Shan (ICTA, 2022)

An Ultra-Energy-Efficient and High Accuracy ECG Classification Processor With SNN Inference Assisted by On-Chip ANN Learning. - Ruixin Mao; Sixu Li; Zhaomin Zhang; Zihan Xia; Jianbiao Xiao; Zixuan Zhu 001; Jiahao Liu; Weiwei Shan; Liang Chang 002; Jun Zhou 017 (IEEE Trans. Biomed. Circuits Syst., 2022)

TEPD: A Compound Timing Detection of Both Data-Transition and Path-Activation for Reliable In-Situ Timing Error Detection and Correction in 28nm CMOS. - Zhengguo Shen; Junyi Qian; Keran Li; Ziyu Li; Lishuo Deng; Weiwei Shan (A-SSCC, 2023)

A 28nm All-Digital, 1.92-7.32mV/LSB, 0.5-2GS/s sample rate, 0-latency Voltage Sensor with Dynamic PVT Calibration for Wide-range Adaptive Voltage Scaling. - Yuxuan Du; Haitao Ge; Zhuo Chen; Kaize Zhou; Zhengguo Shen; Weiwei Shan (CICC, 2023)

A 608nW Near-Microphone Keyword-Spotting Chip Using Real-Point Serial FFT-Based MFCC and Temporal Depthwise Separable CNN in 28nm CMOS. - Cai Li; Haochang Zhi; Long Chen; Kaiyue Yang; Junyi Qian; Zhihao Yan; Lixuan Zhu; Weiwei Shan (CICC, 2023)

Multi-Task Evolutionary to PVT Knowledge Transfer for Analog Integrated Circuit Optimization. - Jintao Li; Haochang Zhi; Weiwei Shan; Yongfu Li 002; Yanhan Zeng; Yun Li 002 (ICCAD, 2023)

A Compact and Robust 28nm CMOS Temperature Sensor with Machine Learning Assisted Design for DVFS SoC. - Yizhi Ding; Haochang Zhi; Jintao Li; Zhuo Chen; Kaiyue Yang; Weiwei Shan (ICTA, 2023)

IVATS: A Leakage Reduction Technique Based on Input Vector Analysis and Transistor Stacking in CMOS Circuits. - Lishuo Deng; Keran Li; Weiwei Shan (ISCAS, 2023)

A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference. - Hao Cai 001; Zhongjian Bian; Yaoru Hou; Yongliang Zhou; Jia-Le Cui; Yanan Guo 004; Xiaoyun Tian; Bo Liu 019; Xin Si; Zhen Wang 019; Jun Yang 006; Weiwei Shan (ISSCC, 2023)

A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs. - An Guo 001; Xin Si; Xi Chen 107; Fangyuan Dong; Xingyu Pu; Dongqi Li; Yongliang Zhou; Lizheng Ren; Yeyang Xue; Xueshan Dong; Hui Gao; Yiran Zhang; et al. (ISSCC, 2023)

Design and analysis of leading one/zero detector based approximate multipliers. - Yuxuan Du; Zhuo Chen; Boyang Cheng; Weiwei Shan (Microelectron. J., 2023)

A 1.23μJ/Inference, All-Digital Shuffle-Type Group-CNN Accelerator in 28nm CMOS With 85.8% Accuracy on CIFAR-10. - Long Chen; Cai Li; Tao Wang; Junyi Qian; Weiwei Shan (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An efficient path delay variability model for wide-voltage-range digital circuits. - Weiwei Shan; Yuqiang Cui; Wentao Dai; Xinning Liu; Jingjing Guo; Peng Cao 002; Jun Yang 006 (Sci. China Inf. Sci., 2023)

AAD-KWS: A Sub-μ W Keyword Spotting Chip With an Acoustic Activity Detector Embedded in MFCC and a Tunable Detection Window in 28-nm CMOS. - Weiwei Shan; Junyi Qian; Lixuan Zhu; Jun Yang 006; Cheng Huang 005; Hao Cai 001 (IEEE J. Solid State Circuits, 2023)

Design of high-efficiency complex multiplier for fault-tolerant computation. - Zhuo Chen; Yuxuan Du; Boyang Cheng; Weiwei Shan (Integr., 2023)

Beyond Eliminating Timing Margin: An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator Without Accuracy Loss. - Zhengguo Shen; Weiwei Shan; Yuxuan Du; Ziyu Li; Jun Yang 006 (IEEE J. Solid State Circuits, 2023)

An All-Digital, 1.92-7.32 mV/LSB, 0.5-2 GS/s Sample Rate, and 0-Latency Prediction Voltage Sensor With Dynamic PVT Calibration for Droop Detection and AVS System. - Yuxuan Du; Junyi Qian; Zhuo Chen; Weiwei Shan (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Make Each Iteration Count. - Yuchen Hu; Ke Xu; Jialin Sun; Xinwei Fang; Weiwei Shan; Xi Wang 009; Zhe Jiang 004 (ACM TUR-C, 2024)

A 28nm 128-kb Exponent- and Mantissa-Computation-InMemory Dual-macro for Floating-point and INT CNNs. - An Guo 001; Xueshan Dong; Fangyuan Dong; Dongqi Li; Yiran Zhang; Jingmin Zhang; Yuchen Tang; Yuhui Shi; Xiao Tan; Bo Liu 019; Weiwei Shan; Hao Cai 001; et al. (A-SSCC, 2024)

An All-digital, 3.68 mV/LSB Voltage Sensor based Droop Prediction and Fast Mitigation System in 28nm CMOS. - Yuxuan Du; Kaize Zhou; Zhuo Chen; Lishuo Deng; Tuo Li; Yan Lu; Weiwei Shan (A-SSCC, 2024)

An Adaptive Wide-Voltage-Range Droop Detection and Protection System Assisted with Timing Error Detection in 28nm CMOS. - Lishuo Deng; Zhengguo Shen; Zhuo Chen; Cai Li; Junyi Qian; Yuxuan Du; Kaize Zhou; Keran Li; Ruidong Li; Tuo Li; Xiaofeng Zou; Weiwei Shan (CICC, 2024)

AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis. - Jintao Li; Haochang Zhi; Ruiyu Lyu; Wangzhen Li; Zhaori Bi; Keren Zhu 001; Yanhan Zeng; Weiwei Shan; Changhao Yan; Fan Yang 001; Yun Li 002; Xuan Zeng 001 (ICCAD, 2024)

MEIC: Re-thinking RTL Debug Automation using LLMs. - Ke Xu; Jialin Sun; Yuchen Hu; Xinwei Fang; Weiwei Shan; Xi Wang 009; Zhe Jiang 004 (ICCAD, 2024)

A 22nm Variation-Tolerant Clock Duty-Cycle Controller for Mitigating Aging-Induced Clock Duty-Cycle Distortion with Path Replica. - Lishuo Deng; Zhiting Li; Changwei Yan; Junyi Qian; Cai Li; Ruidong Li; Tuo Li; Weiwei Shan (ICTA, 2024)

34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs. - An Guo 001; Xi Chen 107; Fangyuan Dong; Jinwu Chen; Zhihang Yuan; Xing Hu 010; Yuanpeng Zhang; Jingmin Zhang; Yuchen Tang; Zhican Zhang; Gang Chen 023; Dawei Yang; et al. (ISSCC, 2024)

14.2 Proactive Voltage Droop Mitigation Using Dual-Proportional-Derivative Control Based on Current and Voltage Prediction Applied to a Multicore Processor in 28nm CMOS. - Weiwei Shan; Kaize Zhou; Keran Li; Yuxuan Du; Zhuo Chen; Junyi Qian; Haitao Ge; Jun Yang 006; Xin Si (ISSCC, 2024)

MEIC: Re-thinking RTL Debug Automation using LLMs. - Ke Xu; Jialin Sun; Yuchen Hu; Xinwei Fang; Weiwei Shan; Xi Wang; Zhe Jiang (CoRR, 2024)

UVLLM: An Automated Universal RTL Verification Framework using LLMs. - Yuchen Hu; Junhao Ye; Ke Xu; Jialin Sun; Shiyue Zhang; Xinyao Jiao; Dingrong Pan; Jie Zhou; Ning Wang 071; Weiwei Shan; Xinwei Fang; Xi Wang 009; et al. (CoRR, 2024)

Ultra-low-power one-hot transmission-gate multiplexer (OTG-MUX) scalable into large fan-in circuits in 28 nm CMOS. - Yuqiang Cui; Weiwei Shan; Peng Cao 002 (Integr., 2024)

FLC-EDC: A Fast Low-Cost Error Detection and Correction Scheme for AVFS System Based on Flip-Flops Resampling in 28-nm CMOS. - Yuqiang Cui; Lishuo Deng; Keran Li; Weiwei Shan (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 0.61-μW Fully Integrated Keyword-Spotting ASIC With Real-Point Serial FFT-Based MFCC and Temporal Depthwise Separable CNN. - Cai Li; Haochang Zhi; Kaiyue Yang; Junyi Qian; Zhihao Yan; Lixuan Zhu; Chao Chen 030; Xi Wang 009; Weiwei Shan (IEEE J. Solid State Circuits, 2024)

Knowledge Transfer Framework for PVT Robustness in Analog Integrated Circuits. - Jintao Li; Yanhan Zeng; Haochang Zhi; Jingci Yang; Weiwei Shan; Yongfu Li 002; Yun Li 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

DSC-TRCP: Dynamically Self-Calibrating Tunable Replica Critical Paths Based Timing Monitoring for Variation Resilient Circuits. - Yuxuan Du; Junyi Qian; Zhengguo Shen; Chengjun Wu; Weiwei Shan; Xi Wang 009 (IEEE J. Solid State Circuits, 2024)

Balancing Objective Optimization and Constraint Satisfaction for Robust Analog Circuit Optimization. - Jintao Li; Haochang Zhi; Jiang Xiao; Yanhan Zeng; Weiwei Shan; Yun Li 002 (ASP-DAC, 2025)

Analog Circuit Transfer Method Across Technology Nodes via Transistor Behavior. - Haochang Zhi; Jintao Li; Yun Li 002; Weiwei Shan (ASP-DAC, 2025)

Efficient Hold Buffer Optimization by Supply Noise-Aware Dynamic Timing Analysis. - Lishuo Deng; Changwei Yan; Cai Li; Zhuo Chen; Weiwei Shan (DATE, 2025)

Variation-Adaptive Negative Bitline and Skip Bitline Pre-charge Scheme for Low-Power SRAM. - Lishuo Deng; Changwei Yan; Yiran Zhang; Xin Si; Weiwei Shan (ISCAS, 2025)

A 250M-2.5GHz Two-Stage Duty-Cycle Corrector with 10%-90% Correction Range and 3-Cycle Correction Latency for Mitigating Aging Effects. - Zhiting Li; Lishuo Deng; Cai Li; Changwei Yan; Zhangrui Qian; Weiwei Shan (ISCAS, 2025)

A 40nm Early-Warning AVFS Design with Path Activation-Based Monitoring Point Optimization. - Cai Li; Zhuoyuan Li; Kaize Zhou; Lishuo Deng; Junyi Qian; Xiaojie Yin; Kana Meng; Weiwei Shan (ISCAS, 2025)

An All-Digital Voltage Droop Detector Utilizing a Multi-Phase Clock assisted Nyquist Counter. - Zhangrui Qian; Kaize Zhou; Yuxuan Du; Zhiting Li; Weiwei Shan (ISCAS, 2025)

14.6 A 28nm 64kb Bit-Rotated Hybrid-CIM Macro with an Embedded Sign-Bit-Processing Array and a Multi-Bit-Fusion Dual-Granularity Cooperative Quantizer. - Xi Chen 107; Shaochen Li; Zhican Zhang; Wentao Zheng; Xiao Tan; Yuchen Tang; Yuhui Shi; Lizheng Ren; Yibo Mai; Feiran Liu; Jinwu Chen; Zhaoyang Zhang; et al. (ISSCC, 2025)

14.7 NeuroPilot: A 28nm, 69.4fJ/node and 0.22ns/node, 32×32 Mimetic-Path-Searching CIM-Macro with Dynamic-Logic Pilot PE and Dual-Direction Searching. - An Guo 001; Jingmin Zhang; Xingyu Pu; Yi Yang 001; Defa Wu; Yuchen Tang; Yuhui Shi; Yinghai Gao; Zhichao Liu; Bo Wang 023; Tianzhu Xiong; Zhaoyang Zhang; et al. (ISSCC, 2025)

14.3 A 28nm 17.83-to-62.84TFLOPS/W Broadcast-Alignment Floating-Point CIM Macro with Non-Two's-Complement MAC for CNNs and Transformers. - Xing Wang; Tianhui Jiao; Yi Yang 001; Shaochen Li; Dongqi Li; An Guo 001; Yuhui Shi; Yuchen Tang; Jinwu Chen; Zhican Zhang; Zhichao Liu; Bo Liu 019; et al. (ISSCC, 2025)

A 4.69-TOPS/W Training, 2.34-μJ/Image Inference On-Chip Training Accelerator With Inference-Compatible Backpropagation and Design Space Exploration in 28-nm CMOS. - Junyi Qian; Haitao Ge; Yicheng Lu; Weiwei Shan (IEEE J. Solid State Circuits, 2025)

A Proactive Droop Mitigation Technique Using Dual-Proportional-Derivative Controller Based on Current and Voltage Prediction. - Kaize Zhou; Weiwei Shan; Keran Li; Zhuo Chen; Haitao Ge; Jun Yang 006 (IEEE J. Solid State Circuits, 2025)

An On-Chip-Training Keyword-Spotting Chip Using Interleaved Pipeline and Computation-in-Memory Cluster in 28-nm CMOS. - Junyi Qian; Cai Li; Long Chen; Ruidong Li; Tuo Li; Peng Cao 002; Xin Si; Weiwei Shan (IEEE Trans. Very Large Scale Integr. Syst., 2025)